-
公开(公告)号：US12170531B2
公开(公告)日：2024-12-17
申请号：US17896994
申请日：2022-08-26
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Nevil Gajera , Mohammed Ebrahim Hargan
Abstract: Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.
-
公开(公告)号：US12072766B2
公开(公告)日：2024-08-27
申请号：US17959412
申请日：2022-10-04
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Joseph M. McCrate
IPC: G06F11/10
CPC classification number: G06F11/1096
Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
-
公开(公告)号：US12210413B2
公开(公告)日：2025-01-28
申请号：US18211881
申请日：2023-06-20
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Marco Sforzin , Paolo Amato , Lingming Yang , Nevil N. Gajera
Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.
-
公开(公告)号：US20240411644A1
公开(公告)日：2024-12-12
申请号：US18813785
申请日：2024-08-23
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Joseph M. McCrate
IPC: G06F11/10
Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
-
公开(公告)号：US20220069207A1
公开(公告)日：2022-03-03
申请号：US17007156
申请日：2020-08-31
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Robert J. Gleixner
Abstract: The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.
-
Patent Agency Ranking
公开(公告)号：US20250077348A1
公开(公告)日：2025-03-06
申请号：US18776730
申请日：2024-07-18
Applicant: Micron Technology, Inc.
Inventor： Antonino Capri' , Daniele Balluchi , Joseph M. McCrate , Graziano Mirichigni , Danilo Caraccio , Marco Sforzin
IPC: G06F11/10
Abstract: A variety of applications can include a memory device implementing one or more caches or buffers integrated with a controller of the memory device to provide post package repair resources. The one or more caches or buffers can be separate from the media subsystem that stores user data for the memory device. Arrangements of the one or more caches or buffers can include the one or more caches or buffers structured between decoder-encoder arrangements of the memory device and the media subsystem of the memory device. Other arrangements of the one or more caches or buffers can include decoder-encoder arrangements of the memory device structured between the one or more caches or buffers and the media subsystem of the memory device. Combinations of arrangements may be implemented. Additional apparatus, systems, and methods are disclosed.
-
公开(公告)号：US20240303159A1
公开(公告)日：2024-09-12
申请号：US18444523
申请日：2024-02-16
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Marco Sforzin , Paolo Amato , Brian M. Twait
IPC: G06F11/10
CPC classification number: G06F11/1076 , G06F11/1004 , G06F11/1016
Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that can correct residual bit errors. The bit errors correctable by the ECC schemes not only include those errors that have been existing in input data used for the RAID process, but also those bit errors may have been propagated due to the existing errors.
-
公开(公告)号：US20210005254A1
公开(公告)日：2021-01-07
申请号：US16460863
申请日：2019-07-02
Applicant: Micron Technology, Inc.
Inventor： Josephine T. Hamada , Mingdong Cui , Joseph M. McCrate , Karthik Sarpatwari , Jessica Chen
Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.
-
公开(公告)号：US20240111629A1
公开(公告)日：2024-04-04
申请号：US17959412
申请日：2022-10-04
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Joseph M. McCrate
IPC: G06F11/10
CPC classification number: G06F11/1096
Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
-
公开(公告)号：US20240004756A1
公开(公告)日：2024-01-04
申请号：US18211881
申请日：2023-06-20
Applicant: Micron technology, Inc.
Inventor： Joseph M. McCrate , Marco Sforzin , Paolo Amato , Lingming Yang , Nevil N. Gajera
CPC classification number: G06F11/1068 , G06F11/0772
Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.014 seconds)
