公开(公告)号：US20250086059A1

公开(公告)日：2025-03-13

申请号：US18778641

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele CONFALONIERI ,  Marco SFORZIN

IPC: G06F11/10 ,  G06F11/07 ,  H03M7/30

Abstract: Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks (LRAID) including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.

公开(公告)号：US20240378113A1

公开(公告)日：2024-11-14

申请号：US18415628

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

公开(公告)号：US20250094278A1

公开(公告)日：2025-03-20

申请号：US18778665

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Emanuele CONFALONIERI ,  Daniele BALLUCHI ,  Danilo CARACCIO ,  Nicola DEL GATTO ,  Rishabh DUBEY

IPC: G06F11/10

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

公开(公告)号：US20240378114A1

公开(公告)日：2024-11-14

申请号：US18415631

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

公开(公告)号：US20240297668A1

公开(公告)日：2024-09-05

申请号：US18415626

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: H03M13/37 ,  G06F11/10 ,  H03M13/15

CPC classification number: H03M13/373 ,  G06F11/1044 ,  H03M13/1575

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

公开(公告)号：US20240413840A1

公开(公告)日：2024-12-12

申请号：US18609417

申请日：2024-03-19

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  DI HSIEN NGU

IPC: H03M13/09 ,  H03K19/173 ,  H03M13/11

Abstract: A system and method for memory error detection and recovery in a decoding system in CXL components is presented. The method includes receiving, into a first decoder within the decoding system, a memory transfer block (MTB) having data and parity information, and having a vertical portion and a horizontal portion, performing error detection and correction on the vertical portion of the MTB using binary hamming code logic within the first decoder; and upon performing error detection and correction in the first decoder, then forwarding MTB to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB using a non-binary hamming code logic within the second decoder such that the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.

公开(公告)号：US20230259424A1

公开(公告)日：2023-08-17

申请号：US17883399

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Paolo AMATO

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F11/1076

Abstract: Provided is a computing system including a memory system in communication with a host, and for storing data therein and the memory system includes a memory having a plurality of memory components and a memory array and coupled to the controller via a memory interface. Each memory component includes a memory cyclic-redundancy-check (CRC) engine that performs a CRC check of data during read and write operations between the host and the memory array. The memory system also includes a controller that has a plurality of controller CRC engines and communicates with the memory components to control data transmission between the memory, the host and the memory array.

公开(公告)号：US20230231573A1

公开(公告)日：2023-07-20

申请号：US17843171

申请日：2022-06-17

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  DI HSIEN NGU

IPC: H03M13/09 ,  H03M13/11 ,  H03K19/173

CPC classification number: H03M13/098 ,  H03M13/1174 ,  H03M13/1171 ,  H03K19/1737

Abstract: A system and method for detecting and correcting memory errors in CXL components is presented. The method includes receiving, into a decoder, a memory transfer block (MTB), wherein the MTB comprises data and parity information, wherein the MTB is arranged in a first dimension and a second dimension. An error checking and a correction function on the MTB is performed using a binary hamming code logic within the decoder in the first dimension. An error checking and a correction function on the MTB is performed using a non-binary hamming code logic within the decoder in the second dimension. Further, the binary hamming code logic and the non-binary hamming code logic perform the error checking on the MTB simultaneously.

公开(公告)号：US20250053506A1

公开(公告)日：2025-02-13

申请号：US18778627

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele CONFALONIERI ,  Marco SFORZIN

IPC: G06F12/02

Abstract: Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether the memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.

公开(公告)号：US20250045153A1

公开(公告)日：2025-02-06

申请号：US18786254

申请日：2024-07-26

Applicant: Micron Technology, Inc.

Inventor： Joseph M. McCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

Abstract: Provided herein is a memory system including logical to physical memory address translation logic to build up a minimum address space containing a memory device address with defects, the translation being based on memory correction attempts. For each correction attempt, the logical address is first translated to a memory device physical address and bit positions at the physical address are compared with an existing error bit pattern to determine if marking should be applied to the memory device. If the bit positions do not match the existing error bit pattern, but errors are corrected from the marked memory device, the existing error bit pattern will be updated to reflect a new error bit pattern.