中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.019 seconds)

    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    1.
    发明申请
    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20230066649A1

    公开(公告)日：2023-03-02

    申请号：US17450729

    申请日：2021-10-13

    Applicant: Micron Technology, Inc.

    Inventor： Erwin E. Yu ,  Surendranath C. Eruvuru ,  Yoshiaki Fukuzumi ,  Tomoko Ogura Iwasaki

    IPC: H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  G11C16/24 ,  G11C7/10 ,  B81B7/02

    Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

    PAGE BUFFER FOR MEMORY DEVICES
    4.
    发明公开
    PAGE BUFFER FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240064988A1

    公开(公告)日：2024-02-22

    申请号：US17900455

    申请日：2022-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Md Zahid Hossain ,  Martin Popp ,  Xiaosong Zhang ,  Surendranath C. Eruvuru ,  Suvra Sarkar ,  Tianqi Xu

    IPC: H01L27/11573 ,  H01L27/11526

    CPC classification number: H01L27/11573 ,  H01L27/11526

    Abstract: A variety of applications can include apparatus having a memory device structured with a circuit under array (CuA) architecture. A page buffer region in the CuA can be formed with a periphery region that is horizontally adjacent to the page buffer region. Contacts to gates for transistors in the page buffer region can be formed to land only on these gates, separating and electrically isolating the contacts and associated gates from each other in the page buffer region. Contacts to gates for transistors in the periphery region can be formed to land on conductive regions disposed on gates for transistors in the periphery region.

    Non-orthogonal slotted vias for semiconductor devices and associated systems and methods
    5.
    发明授权
    Non-orthogonal slotted vias for semiconductor devices and associated systems and methods 有权

    公开(公告)号：US11545433B2

    公开(公告)日：2023-01-03

    申请号：US17121645

    申请日：2020-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Raja Kumar Varma Manthena ,  Surendranath C. Eruvuru

    IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/115

    Abstract: Semiconductor devices with slotted vias, and associated systems and methods, are disclosed herein. In one embodiment, a routing region of the semiconductor device includes a set of slotted vias arranged in a non-orthogonal array pattern. Further, patterns of metal lines associated with the set of slotted vias are drawn to align and/or overlap with the slotted vias. As a result, the metal lines may include zig-zag patterns within the routing region. Further, edges of the slotted vias may have a staircase pattern with sets of horizontal and vertical line segments such that a combination of the horizontal and vertical line segments can orient the slotted vias in a non-orthogonal direction.

    MEMORY DEVICES INCLUDING PAD STRUCTURES
    6.
    发明申请
    MEMORY DEVICES INCLUDING PAD STRUCTURES 有权

    公开(公告)号：US20250098159A1

    公开(公告)日：2025-03-20

    申请号：US18969510

    申请日：2024-12-05

    Applicant: Micron Technology, Inc.

    Inventor： Erwin E. Yu ,  Michele Piccardi ,  Surendranath C. Eruvuru

    IPC: H10B41/27 ,  B81B1/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H01L27/092 ,  H10B43/27

    Abstract: A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.

    MEMORY DEVICES AND ELECTRONIC SYSTEMS
    7.
    发明申请
    MEMORY DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20250008727A1

    公开(公告)日：2025-01-02

    申请号：US18886735

    申请日：2024-09-16

    Applicant: Micron Technology, Inc.

    Inventor： Erwin E. Yu ,  Surendranath C. Eruvuru ,  Yoshiaki Fukuzumi ,  Tomoko Ogura Iwasaki

    IPC: H10B41/41 ,  B81B7/02 ,  G11C7/10 ,  G11C16/24 ,  H10B41/20 ,  H10B43/20 ,  H10B43/40

    Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

    ANTENNA PROTECTION ON DUMMY METAL FILLS
    8.
    发明公开
    ANTENNA PROTECTION ON DUMMY METAL FILLS 审中-公开

    公开(公告)号：US20230402407A1

    公开(公告)日：2023-12-14

    申请号：US17752647

    申请日：2022-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Hao Chen ,  Raja Kumar Varma Manthena ,  Surendranath C. Eruvuru

    IPC: H01L23/60 ,  H01L23/58

    CPC classification number: H01L23/60 ,  H01L23/585

    Abstract: A memory device can include a semiconductor substrate having a plurality of active semiconductor devices. The memory device can include a plurality of metallization layers disposed over the semiconductor substrate, where each of the plurality of metallization layers is separated from adjacent metallization layers by an interlayer dielectric. The memory device also includes a dummy metal fill disposed in a metallization layer. The dummy metal fill can be connected to a discharge path for dissipating a charge build up in the dummy metal fill to minimize antenna effects. In some embodiments, the discharge path can include the semiconductor substrate, which can be an electrical drain. The antenna protected dummy metal fill ensures is configured such that any accumulated charge during the fabrication process is discharged to the electric drain.

Patent Agency Ranking