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    NON-ORTHOGONAL SLOTTED VIAS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS
    1.
    发明申请
    NON-ORTHOGONAL SLOTTED VIAS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20220189874A1

    公开(公告)日：2022-06-16

    申请号：US17121645

    申请日：2020-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Raja Kumar Varma Manthena ,  Surendranath C. Eruvuru

    IPC: H01L23/528 ,  H01L23/522

    Abstract: Semiconductor devices with slotted vias, and associated systems and methods, are disclosed herein. In one embodiment, a routing region of the semiconductor device includes a set of slotted vias arranged in a non-orthogonal array pattern. Further, patterns of metal lines associated with the set of slotted vias are drawn to align and/or overlap with the slotted vias. As a result, the metal lines may include zig-zag patterns within the routing region. Further, edges of the slotted vias may have a staircase pattern with sets of horizontal and vertical line segments such that a combination of the horizontal and vertical line segments can orient the slotted vias in a non-orthogonal direction.

    Non-orthogonal slotted vias for semiconductor devices and associated systems and methods
    2.
    发明授权
    Non-orthogonal slotted vias for semiconductor devices and associated systems and methods 有权

    公开(公告)号：US11545433B2

    公开(公告)日：2023-01-03

    申请号：US17121645

    申请日：2020-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Raja Kumar Varma Manthena ,  Surendranath C. Eruvuru

    IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/115

    Abstract: Semiconductor devices with slotted vias, and associated systems and methods, are disclosed herein. In one embodiment, a routing region of the semiconductor device includes a set of slotted vias arranged in a non-orthogonal array pattern. Further, patterns of metal lines associated with the set of slotted vias are drawn to align and/or overlap with the slotted vias. As a result, the metal lines may include zig-zag patterns within the routing region. Further, edges of the slotted vias may have a staircase pattern with sets of horizontal and vertical line segments such that a combination of the horizontal and vertical line segments can orient the slotted vias in a non-orthogonal direction.

    APPARATUSES AND MEMORY DEVICES INCLUDING SLOT STRUCTURES EXTENDING THROUGH STACK STRUCTURES
    3.
    发明申请
    APPARATUSES AND MEMORY DEVICES INCLUDING SLOT STRUCTURES EXTENDING THROUGH STACK STRUCTURES 有权

    公开(公告)号：US20220406807A1

    公开(公告)日：2022-12-22

    申请号：US17822036

    申请日：2022-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Raja Kumar Varma Manthena ,  Anilkumar Chandolu

    IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

    Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    4.
    发明申请
    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20250069950A1

    公开(公告)日：2025-02-27

    申请号：US18948269

    申请日：2024-11-14

    Applicant: Micron Technology, Inc.

    Inventor： Raja Kumar Varma Manthena ,  Paolo Tessariol

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

    Abstract: A microelectronic device comprises a stack structure, first dielectric-filled trenches extending vertically through the stack structure, and at least one second dielectric-filled trench intersecting the first dielectric-filled trenches. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The first dielectric-filled trenches divide the stack structure into blocks and extend horizontally in a first direction. At least one second dielectric-filled trench extends horizontally in a second direction orthogonal to the first direction. At least one second dielectric-filled trench has boundaries defined by at least one staircase structure having steps defined by horizontal ends of the tiers in the first direction. Memory devices and electronic systems are also described.

    ANTENNA PROTECTION ON DUMMY METAL FILLS
    7.
    发明公开
    ANTENNA PROTECTION ON DUMMY METAL FILLS 审中-公开

    公开(公告)号：US20230402407A1

    公开(公告)日：2023-12-14

    申请号：US17752647

    申请日：2022-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Hao Chen ,  Raja Kumar Varma Manthena ,  Surendranath C. Eruvuru

    IPC: H01L23/60 ,  H01L23/58

    CPC classification number: H01L23/60 ,  H01L23/585

    Abstract: A memory device can include a semiconductor substrate having a plurality of active semiconductor devices. The memory device can include a plurality of metallization layers disposed over the semiconductor substrate, where each of the plurality of metallization layers is separated from adjacent metallization layers by an interlayer dielectric. The memory device also includes a dummy metal fill disposed in a metallization layer. The dummy metal fill can be connected to a discharge path for dissipating a charge build up in the dummy metal fill to minimize antenna effects. In some embodiments, the discharge path can include the semiconductor substrate, which can be an electrical drain. The antenna protected dummy metal fill ensures is configured such that any accumulated charge during the fabrication process is discharged to the electric drain.

    LATERAL ETCH STOPS FOR ACCESS LINE FORMATION IN A MEMORY DIE
    9.
    发明公开
    LATERAL ETCH STOPS FOR ACCESS LINE FORMATION IN A MEMORY DIE 审中-公开

    公开(公告)号：US20240040787A1

    公开(公告)日：2024-02-01

    申请号：US17876326

    申请日：2022-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Raja Kumar Varma Manthena ,  Yoshiaki Fukuzumi

    IPC: H01L27/1157 ,  H01L27/11531 ,  H01L27/11529 ,  G11C16/06

    CPC classification number: H01L27/1157 ,  H01L27/11531 ,  H01L27/11529 ,  G11C16/06

    Abstract: Methods, systems, and devices for lateral etch stops for access line formation in a memory die are described. A memory die may be formed with isolation regions that provide an etch stop to limit the extent of voids formed by removing a sacrificial material between layers of a dielectric region. For example, first trenches may be formed through a stack of alternating layers of a dielectric material and a sacrificial material, in which one or more materials may formed. Second trenches may be formed between a first trench and an array portion of the memory die, or between pairs of the first trenches, which may support the removal of at least a portion of the sacrificial material to form voids for access line formation. However, the materials formed in the first trenches may provide a boundary, or a restriction zone, that limits an extent of the material removal operation.

    ISOLATION REGIONS WITHIN A MEMORY DIE
    10.
    发明公开
    ISOLATION REGIONS WITHIN A MEMORY DIE 审中-公开

    公开(公告)号：US20240038577A1

    公开(公告)日：2024-02-01

    申请号：US17815915

    申请日：2022-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Raja Kumar Varma Manthena ,  Yoshiaki Fukuzumi

    IPC: H01L21/762 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/311

    CPC classification number: H01L21/76224 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/31144

    Abstract: Methods, systems, and devices for isolation regions within a memory die are described. During fabrication, memory pillars may be formed through a stack of material in a plurality regions of a memory die. In some cases, a first plurality of trenches extending in a first direction and a second plurality of trenches extending in a second direction may be formed through the stack of material (e.g., interposed between the plurality of regions). Additionally or alternatively, first voids may be formed via the first plurality of trenches, and a dielectric material may be deposited in the first voids and the first plurality of trenches, forming first isolation regions. Then, second voids may be formed via the second plurality of trenches, and a dielectric material may be deposited in the second voids and the second plurality of trenches, forming second isolation regions.

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