公开(公告)号：US20140139270A1

公开(公告)日：2014-05-22

申请号：US13928376

申请日：2013-06-26

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chieh-An Lin

IPC: H03K3/011

CPC classification number: G09G3/00 ,  G09G2300/0838 ,  G09G2300/0871 ,  G09G2310/0213 ,  G09G2310/0289 ,  G09G2330/045

Abstract: A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC.

Abstract translation: 提供面板驱动器集成电路（IC）和面板驱动器IC的冷却方法。 面板驱动器IC包括数据编码器，电平转换器，数模转换器（DAC），重排电路和输出缓冲器。 数据编码器接收并选择性地改变用于输出到电平移位器的原始数据。 电平移位器的输入端子和输出端子分别耦合到数据编码器的输出端子和DAC的数据输入端子。 重排电路的输出端分别耦合到DAC的参考电压输入端，以提供不同的参考电压。 重排电路根据数据编码器的操作相应地重新排列参考电压的顺序。 输出缓冲器的输入端耦合到DAC的输出端。

公开(公告)号：US20140133058A1

公开(公告)日：2014-05-15

申请号：US13865210

申请日：2013-04-18

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Ju-Lin Huang ,  Che-Lun Hsu ,  Jhih-Siou Cheng ,  Chun-Yung Cho

IPC: H02H9/02

CPC classification number: H02H9/046 ,  G09G3/20 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2330/028 ,  G09G2330/04 ,  G09G2330/06 ,  H03M1/00 ,  H03M1/0827 ,  H03M1/808

Abstract: A driving circuit includes several first electrostatic current limiting resistors and several digital to analog converter (DAC) units. First ends of these first electrostatic current limiting resistors common coupled to a global path to receive a reference voltage. These DAC units respectively coupled to second ends of the first electrostatic current limiting resistors one-on-one to receive the reference voltage through the first electrostatic current limiting resistors.

Abstract translation: 驱动电路包括几个第一静电电流限制电阻器和几个数模转换器（DAC）单元。 这些第一静电电流限制电阻的第一端公共耦合到全局路径以接收参考电压。 这些DAC单元分别耦合到第一静电电流限制电阻器的第二端，以通过第一静电电流限制电阻器接收参考电压。

公开(公告)号：USRE47432E1

公开(公告)日：2019-06-11

申请号：US15186555

申请日：2016-06-20

Applicant: NOVATEK Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Keko-Chun Liang ,  Chun-Yung Cho ,  Cheng-Hung Chen

IPC: H03B1/00 ,  G05F3/16

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

公开(公告)号：US08917121B2

公开(公告)日：2014-12-23

申请号：US13717648

申请日：2012-12-17

Applicant: NOVATEK Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Keko-Chun Liang ,  Chun-Yung Cho ,  Cheng-Hung Chen

IPC: H03B1/00 ,  G05F3/16

CPC classification number: G05F3/16 ,  G05F3/205

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

Abstract translation: 输出级电路包括：第一晶体管，包括耦合到第一节点的第一端子，耦合到输出端子的第二端子，耦合到用于接收输入电压的输入端子的第三端子，以及耦合到第一端子的第四端子 用于接收第一电压的第一电源端子; 第二晶体管，包括耦合到第二节点的第一端子，耦合到输出端子的第二端子，耦合到输入端子用于接收输入电压的第三端子和耦合到地的第四端子; 以及耦合到输出端子以提供恒定电流的电流源。

公开(公告)号：US20140218111A1

公开(公告)日：2014-08-07

申请号：US14016136

申请日：2013-09-02

Applicant: Novatek Microelectronics Corp.

Inventor： Chieh-An Lin ,  Chun-Yung Cho ,  Ju-Lin Huang

IPC: H03F3/45

CPC classification number: H03F3/45076 ,  H03F3/3022 ,  H03F3/45192 ,  H03F2200/234 ,  H03F2203/45116

Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.

Abstract translation: 提供了构造成驱动负载的运算放大器电路。 运算放大器电路包括输出级模块。 输出级模块包括检测电路和输出级电路。 检测电路被配置为基于当前输入电压和电流输出电压的比较结果来检测电流输出电压和先前的输出电压。 检测电路基于检测结果增强负载的输出级电路的充电容量或放电容量。 此外，还提供了一种用于增强运算放大器电路的驱动能力的方法。

公开(公告)号：US20140004725A1

公开(公告)日：2014-01-02

申请号：US13674903

申请日：2012-11-12

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

IPC: H01R12/51

CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

Abstract: A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure.

Abstract translation: 芯片封装结构包括封装体，第一引线和第二引线。 嵌入在封装体内的元件包括具有至少一个第一连接端子，至少一个ESD保护电路的至少一个第二连接端子，至少一个第三连接端子和至少一个互连结构的芯电路。 互连结构电连接到第二连接端子和第三连接端子。 封装主体上的第一引线电连接到第二连接端子和外部电路。 封装体上的第二引线电连接第一连接端子和第三连接端子。 第二个引线和第一个引线在结构上是分开的。

公开(公告)号：US09997119B2

公开(公告)日：2018-06-12

申请号：US14339753

申请日：2014-07-24

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chieh-An Lin ,  Chun-Yung Cho ,  Jhih-Siou Cheng

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0291

Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a positive polarity buffer, a negative polarity buffer. The positive polarity buffer receives a first supply voltage and a second supply voltage to output a positive reference voltage to a positive resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.

公开(公告)号：US09467108B2

公开(公告)日：2016-10-11

申请号：US14741469

申请日：2015-06-17

Applicant: Novatek Microelectronics Corp.

Inventor： Chieh-An Lin ,  Chun-Yung Cho ,  Ju-Lin Huang

IPC: H03F3/45 ,  H03F3/30

CPC classification number: H03F3/45076 ,  H03F3/3022 ,  H03F3/45192 ,  H03F2200/234 ,  H03F2203/45116

Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.

公开(公告)号：US09245857B2

公开(公告)日：2016-01-26

申请号：US14726613

申请日：2015-06-01

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/60 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H02H9/02

CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.

Abstract translation: 芯片封装结构包括封装体。 封装体包括核心电路和静电放电保护电路。 第一连接端子电连接到核心电路。 第二连接端子电连接到静电放电保护电路。 电连接到静电放电保护电路的第一互连结构，第二连接端子和第三连接端子。 第一引线将第二连接端子和外部电路电连接。 第二引线电连接第一连接端子和第三连接端子。 第二个领先者和第一个领先者基本上是分开的。

公开(公告)号：US09106189B2

公开(公告)日：2015-08-11

申请号：US14016136

申请日：2013-09-02

Applicant: Novatek Microelectronics Corp.

Inventor： Chieh-An Lin ,  Chun-Yung Cho ,  Ju-Lin Huang

IPC: H03F3/45 ,  H03F3/30

CPC classification number: H03F3/45076 ,  H03F3/3022 ,  H03F3/45192 ,  H03F2200/234 ,  H03F2203/45116

Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.

Abstract translation: 提供了构造成驱动负载的运算放大器电路。 运算放大器电路包括输出级模块。 输出级模块包括检测电路和输出级电路。 检测电路被配置为基于当前输入电压和电流输出电压的比较结果来检测电流输出电压和先前的输出电压。 检测电路基于检测结果增强负载的输出级电路的充电容量或放电容量。 此外，还提供了一种用于增强运算放大器电路的驱动能力的方法。