公开(公告)号：US20140375620A1

公开(公告)日：2014-12-25

申请号：US14054853

申请日：2013-10-16

Applicant: Novatek Microelectronics Corp.

Inventor： Cheng-Hung Chen ,  Jen-Chieh Hu ,  Ju-Lin Huang ,  Yi-Chuan Liu ,  Jhih-Siou Cheng

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G3/20 ,  G09G2310/0275 ,  G09G2320/041 ,  G09G2330/045

Abstract: A display apparatus and a source driver thereof are disclosed. The source driver includes a temperature sensor and a power switch. The temperature sensor is configured to measure a first working temperature of the source driver, and generate an over-temperature protection enable signal by comparing the first working temperature with a preset temperature. The power switch is coupled to a power transmission path for a core circuit of the source driver to receive an operating power, and configured to turn on or cut off the power transmission path according to the over-temperature protection enable signal.

Abstract translation: 公开了一种显示装置及其源驱动器。 源驱动器包括温度传感器和电源开关。 温度传感器被配置为测量源极驱动器的第一工作温度，并且通过将第一工作温度与预设温度进行比较来产生过温保护使能信号。 电源开关耦合到用于源极驱动器的核心电路的电力传输路径以接收工作电力，并且被配置为根据过温度保护使能信号接通或切断电力传输路径。

公开(公告)号：US08823440B2

公开(公告)日：2014-09-02

申请号：US13792245

申请日：2013-03-11

Applicant: Novatek Microelectronics Corp.

Inventor： Cheng-Hung Chen ,  Ju-Lin Huang ,  Keko-Chun Liang

IPC: H03L5/00

CPC classification number: H03K3/012 ,  H03K3/356182

Abstract: A level shifting circuit with dynamic control includes a dynamic controller and a level shifter. The dynamic controller outputs a dynamic voltage and an output data signal. The level shifter under control by the dynamic controller includes an input signal receiver, an output signal generator, and a bias current controller, which are coupled in series between a ground voltage and a high level voltage. The input signal receiver receives the output data signal of the dynamic controller and the output signal generator produces a level-shifted data signal according to the input data signal. The bias current controller controlled by the dynamic voltage is at a first current-output capability when the level-shifted data signal is at a stable stage and at a second current-output capability when the level-shifted data signal is at an unstable stage. The first current-output capability is greater than the second current-output capability.

Abstract translation: 具有动态控制的电平移动电路包括动态控制器和电平转换器。 动态控制器输出动态电压和输出数据信号。 由动态控制器控制的电平移位器包括输入信号接收器，输出信号发生器和偏置电流控制器，它们串联在接地电压和高电平电压之间。 输入信号接收器接收动态控制器的输出数据信号，输出信号发生器根据输入数据信号产生电平移位数据信号。 当电平移位数据信号处于不稳定阶段时，当电平移位数据信号处于稳定级并处于第二电流输出能力时，由动态电压控制的偏置电流控制器处于第一电流输出能力。 第一个电流输出能力大于第二个电流输出能力。

公开(公告)号：US09245857B2

公开(公告)日：2016-01-26

申请号：US14726613

申请日：2015-06-01

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/60 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H02H9/02

CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.

Abstract translation: 芯片封装结构包括封装体。 封装体包括核心电路和静电放电保护电路。 第一连接端子电连接到核心电路。 第二连接端子电连接到静电放电保护电路。 电连接到静电放电保护电路的第一互连结构，第二连接端子和第三连接端子。 第一引线将第二连接端子和外部电路电连接。 第二引线电连接第一连接端子和第三连接端子。 第二个领先者和第一个领先者基本上是分开的。

公开(公告)号：US20130241631A1

公开(公告)日：2013-09-19

申请号：US13717648

申请日：2012-12-17

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Ju-Lin Huang ,  Keko-Chun Liang ,  Chun-Yung Cho ,  Cheng-Hung Chen

IPC: G05F3/16

CPC classification number: G05F3/16 ,  G05F3/205

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

Abstract translation: 输出级电路包括：第一晶体管，包括耦合到第一节点的第一端子，耦合到输出端子的第二端子，耦合到用于接收输入电压的输入端子的第三端子，以及耦合到第一端子的第四端子 用于接收第一电压的第一电源端子; 第二晶体管，包括耦合到第二节点的第一端子，耦合到输出端子的第二端子，耦合到输入端子用于接收输入电压的第三端子和耦合到地的第四端子; 以及耦合到输出端子以提供恒定电流的电流源。

公开(公告)号：US20150262943A1

公开(公告)日：2015-09-17

申请号：US14726613

申请日：2015-06-01

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

IPC: H01L23/60 ,  H02H9/02 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.

Abstract translation: 芯片封装结构包括封装体。 封装体包括核心电路和静电放电保护电路。 第一连接端子电连接到核心电路。 第二连接端子电连接到静电放电保护电路。 电连接到静电放电保护电路的第一互连结构，第二连接端子和第三连接端子。 第一引线将第二连接端子和外部电路电连接。 第二引线电连接第一连接端子和第三连接端子。 第二个领先者和第一个领先者基本上是分开的。

公开(公告)号：US09048243B2

公开(公告)日：2015-06-02

申请号：US13674903

申请日：2012-11-12

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/60 ,  H05K9/00 ,  H01L25/065

CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

Abstract: A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure.

Abstract translation: 芯片封装结构包括封装体，第一引线和第二引线。 嵌入在封装体内的元件包括具有至少一个第一连接端子，至少一个ESD保护电路的至少一个第二连接端子，至少一个第三连接端子和至少一个互连结构的芯电路。 互连结构电连接到第二连接端子和第三连接端子。 封装主体上的第一引线电连接到第二连接端子和外部电路。 封装体上的第二引线电连接第一连接端子和第三连接端子。 第二个引线和第一个引线在结构上是分开的。

公开(公告)号：US20140015587A1

公开(公告)日：2014-01-16

申请号：US13792245

申请日：2013-03-11

Applicant: NOVATEK MICROELECTRONICS CORP

Inventor： Cheng-Hung Chen ,  Ju-Lin Huang ,  Keko-Chun Liang

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356182

Abstract: A level shifting circuit with dynamic control includes a dynamic controller and a level shifter. The dynamic controller outputs a dynamic voltage and an output data signal. The level shifter under control by the dynamic controller includes an input signal receiver, an output signal generator, and a bias current controller, which are coupled in series between a ground voltage and a high level voltage. The input signal receiver receives the output data signal of the dynamic controller and the output signal generator produces a level-shifted data signal according to the input data signal. The bias current controller controlled by the dynamic voltage is at a first current-output capability when the level-shifted data signal is at a stable stage and at a second current-output capability when the level-shifted data signal is at an unstable stage. The first current-output capability is greater than the second current-output capability.

Abstract translation: 具有动态控制的电平移动电路包括动态控制器和电平转换器。 动态控制器输出动态电压和输出数据信号。 由动态控制器控制的电平移位器包括输入信号接收器，输出信号发生器和偏置电流控制器，它们串联在接地电压和高电平电压之间。 输入信号接收器接收动态控制器的输出数据信号，输出信号发生器根据输入数据信号产生电平移位数据信号。 当电平移位数据信号处于不稳定阶段时，当电平移位数据信号处于稳定级并处于第二电流输出能力时，由动态电压控制的偏置电流控制器处于第一电流输出能力。 第一个电流输出能力大于第二个电流输出能力。

公开(公告)号：USRE47432E1

公开(公告)日：2019-06-11

申请号：US15186555

申请日：2016-06-20

Applicant: NOVATEK Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Keko-Chun Liang ,  Chun-Yung Cho ,  Cheng-Hung Chen

IPC: H03B1/00 ,  G05F3/16

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

公开(公告)号：US08917121B2

公开(公告)日：2014-12-23

申请号：US13717648

申请日：2012-12-17

Applicant: NOVATEK Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Keko-Chun Liang ,  Chun-Yung Cho ,  Cheng-Hung Chen

IPC: H03B1/00 ,  G05F3/16

CPC classification number: G05F3/16 ,  G05F3/205

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

Abstract translation: 输出级电路包括：第一晶体管，包括耦合到第一节点的第一端子，耦合到输出端子的第二端子，耦合到用于接收输入电压的输入端子的第三端子，以及耦合到第一端子的第四端子 用于接收第一电压的第一电源端子; 第二晶体管，包括耦合到第二节点的第一端子，耦合到输出端子的第二端子，耦合到输入端子用于接收输入电压的第三端子和耦合到地的第四端子; 以及耦合到输出端子以提供恒定电流的电流源。

公开(公告)号：US20140004725A1

公开(公告)日：2014-01-02

申请号：US13674903

申请日：2012-11-12

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

IPC: H01R12/51

CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

Abstract: A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure.

Abstract translation: 芯片封装结构包括封装体，第一引线和第二引线。 嵌入在封装体内的元件包括具有至少一个第一连接端子，至少一个ESD保护电路的至少一个第二连接端子，至少一个第三连接端子和至少一个互连结构的芯电路。 互连结构电连接到第二连接端子和第三连接端子。 封装主体上的第一引线电连接到第二连接端子和外部电路。 封装体上的第二引线电连接第一连接端子和第三连接端子。 第二个引线和第一个引线在结构上是分开的。