公开(公告)号：US11137815B2

公开(公告)日：2021-10-05

申请号：US15922579

申请日：2018-03-15

Applicant: NVIDIA Corporation

Inventor： Amit Pabalkar

IPC: G06F1/3287 ,  G06F1/3228 ,  G06T1/20

Abstract: Embodiments of the present invention provide methods and apparatus for metering GPU workload in real time. Metering of the GPU workload is performed by a Workload Metering (WLM) algorithm implemented in software or firmware that calculates a duty cycle for the graphics engine. The duty cycle forces the graphics engine to transition from a busy state to an idle state periodically based on measured power consumption, and engages race-to-sleep techniques to place the engine or engines in a low power state during the forced idle times, thereby reducing the overall power draw of the GPU to meet a predetermined power budget. According to some embodiments, the WLM algorithm is deployed on a microcontroller of a power management unit (PMU).

公开(公告)号：US10996725B2

公开(公告)日：2021-05-04

申请号：US16108006

申请日：2018-08-21

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith Li ,  Thomas E. Dewey ,  Arthur Chen ,  Simon Lai ,  Amit Pabalkar ,  Santosh Nayak

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/4401 ,  G06F1/08

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

公开(公告)号：US20190286214A1

公开(公告)日：2019-09-19

申请号：US15922579

申请日：2018-03-15

Applicant: NVIDIA Corporation

Inventor： Amit Pabalkar

IPC: G06F1/32 ,  G06T1/20

Abstract: Embodiments of the present invention provide methods and apparatus for metering GPU workload in real time. Metering of the GPU workload is performed by a Workload Metering (WLM) algorithm implemented in software or firmware that calculates a duty cycle for the graphics engine. The duty cycle forces the graphics engine to transition from a busy state to an idle state periodically based on measured power consumption, and engages race-to-sleep techniques to place the engine or engines in a low power state during the forced idle times, thereby reducing the overall power draw of the GPU to meet a predetermined power budget. According to some embodiments, the WLM algorithm is deployed on a microcontroller of a power management unit (PMU).

公开(公告)号：US11886262B2

公开(公告)日：2024-01-30

申请号：US17306654

申请日：2021-05-03

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith Li ,  Thomas E. Dewey ,  Arthur Chen ,  Simon Lai ,  Amit Pabalkar ,  Santosh Nayak

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/4401 ,  G06F1/08

CPC classification number: G06F1/26 ,  G06F1/08 ,  G06F9/4411

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

公开(公告)号：US11106261B2

公开(公告)日：2021-08-31

申请号：US16179620

申请日：2018-11-02

Applicant: NVIDIA Corporation

Inventor： Aniket Naik ,  Siddharth Bhargav ,  Bardia Zandian ,  Narayan Kulshrestha ,  Amit Pabalkar ,  Arvind Gopalakrishnan ,  Justin Tai ,  Sachin Satish Idgunji

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/3206 ,  G06F9/50 ,  G06F1/3296 ,  G06F1/28 ,  G06N20/00 ,  G06N5/04

Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.