公开(公告)号：US12019498B2

公开(公告)日：2024-06-25

申请号：US16175232

申请日：2018-10-30

Applicant: NVIDIA Corporation

Inventor： Thomas E. Dewey ,  Narayan Kulshrestha ,  Ramachandiran V ,  Sachin Idgunji ,  Lordson Yue

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/42 ,  G06F15/78 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F1/3278 ,  G06F1/3296 ,  G06F13/4221 ,  G06F15/7807 ,  G06T1/20 ,  G06T15/005 ,  G06F2213/0026

Abstract: An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

公开(公告)号：US11886262B2

公开(公告)日：2024-01-30

申请号：US17306654

申请日：2021-05-03

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith Li ,  Thomas E. Dewey ,  Arthur Chen ,  Simon Lai ,  Amit Pabalkar ,  Santosh Nayak

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/4401 ,  G06F1/08

CPC classification number: G06F1/26 ,  G06F1/08 ,  G06F9/4411

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

公开(公告)号：US20230213999A1

公开(公告)日：2023-07-06

申请号：US17961430

申请日：2022-10-06

Applicant: NVIDIA CORPORATION

Inventor： Thomas E. Dewey ,  Michael IRWIN ,  Simon LAI ,  Sau Yan Keith LI

IPC: G06F1/324 ,  G06F1/3287 ,  G06F1/20

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F1/20

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises determining a first value for a first power setting associated with a first processor based on a sound level generated by the multi-processor computing device; determining a second value for the first power setting based on a power consumption level of the multi-processor computing device; comparing the first value to the second value; and causing the first processor to perform one or more operations based on the lesser of the first value and the second value.

公开(公告)号：US10996725B2

公开(公告)日：2021-05-04

申请号：US16108006

申请日：2018-08-21

Applicant: NVIDIA Corporation

Inventor： Sau Yan Keith Li ,  Thomas E. Dewey ,  Arthur Chen ,  Simon Lai ,  Amit Pabalkar ,  Santosh Nayak

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/4401 ,  G06F1/08

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

公开(公告)号：US12130687B2

公开(公告)日：2024-10-29

申请号：US17961440

申请日：2022-10-06

Applicant: NVIDIA CORPORATION

Inventor： Thomas E. Dewey ,  Michael Irwin ,  Simon Lai ,  Sau Yan Keith Li

IPC: G06F1/00 ,  G05B13/02 ,  G06F1/20 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3287

CPC classification number: G06F1/3234 ,  G05B13/028 ,  G06F1/20 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3287

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.

公开(公告)号：US10852811B2

公开(公告)日：2020-12-01

申请号：US16049916

申请日：2018-07-31

Applicant: NVIDIA Corporation

Inventor： Sachin Idgunji ,  Ben Pei En Tsai ,  Jun (Alex) Gu ,  James Reilley ,  Thomas E. Dewey

IPC: G06F1/3296 ,  G06T1/20 ,  H04J3/00

Abstract: An integrated circuit such as, for example a graphics processing unit (GPU), having an on-chip analog to digital converter (ADC) for use in overcurrent protection of the chip is described, where the overcurrent protection response times are substantially faster than techniques with external ADC. A system-on-chip (SoC) includes the integrated circuit and a multiplexer arranged externally to the chip having the ADC, where the multiplexer provides the ADC with a data stream of sampling information from a plurality of power sources. Methods for overcurrent protection using an on-chip ADC are also described.