公开(公告)号：US20240267056A1

公开(公告)日：2024-08-08

申请号：US18106803

申请日：2023-02-07

Applicant: NXP B.V.

Inventor： Erik Olieman ,  Alphons Litjes ,  Robert van Veldhoven

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/08

CPC classification number: H03M1/124 ,  H03M1/0626 ,  H03M1/08

Abstract: A system and method of analog to digital conversion including an adjustable ADC, FIR filter circuitry, and a noise setting controller. The ADC samples an analog input signal to provide digital samples at a sample rate that is Y times an output rate of output digital values. The FIR filter circuitry includes Y taps with Y corresponding coefficients and is configured to filter the digital samples from the ADC and to provide filtered digital samples at the sample rate. decimation circuitry may be included to decimate the filtered digital samples by Y to provide the output digital values. The noise setting controller provides an adjustment value to the ADC to adjust noise contribution of the digital samples provided by the ADC based on corresponding coefficients of the FIR filter circuitry. The ADC is adjusted to reduce noise contribution of digital samples that correspond with higher FIR filter coefficients.

公开(公告)号：US20230231566A1

公开(公告)日：2023-07-20

申请号：US17577501

申请日：2022-01-18

Applicant: NXP B.V.

Inventor： Erik Olieman ,  Rene Verlinden ,  Helmut Kranabenter

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO− signals, and outputs a second controlled LO signal output to a sense circuit.

公开(公告)号：US20190158108A1

公开(公告)日：2019-05-23

申请号：US16122637

申请日：2018-09-05

Applicant: NXP B.V.

Inventor： Robert Van Veldhoven ,  Alphons Litjes ,  Erik Olieman

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/06 ,  H03M1/36

Abstract: The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.

公开(公告)号：US20250141457A1

公开(公告)日：2025-05-01

申请号：US18384823

申请日：2023-10-27

Applicant: NXP B.V.

Inventor： Michael Todd Berens ,  Alphons Litjes ,  Erik Olieman

IPC: H03M1/06

Abstract: A SAR ADC includes a DAC, a comparator and SAR circuitry, where the DAC includes MSBs encoded with first capacitors; a mismatch error shaping capacitor coupled to the MSBs; LSBs encoded with second capacitors, where a first switch set couples bottom capacitor plates of the first capacitors and the mismatch error shaping capacitor to receive an analog input voltage, a high reference voltage, or a low reference voltage in response to first DAC feedback control signals, wherein a second switch set couples bottom capacitor plates of the second capacitors to receive the high reference voltage or the low reference voltage in response to second DAC feedback control signals, and wherein the SAR circuitry is configured to feedback a mismatch error value from a previous SAR conversion cycle to the LSBs sub-DAC during a current sampling cycle.

公开(公告)号：US20240405780A1

公开(公告)日：2024-12-05

申请号：US18205250

申请日：2023-06-02

Applicant: NXP B.V.

Inventor： Alphons Litjes ,  Erik Olieman

IPC: H03M1/06

Abstract: An analog to digital converter including a digital to analog converter (DAC), a comparator, and a controller. The DAC includes a sample node and a capacitor array controlled by a digital control input. The comparator compares a voltage of the sample node with a reference voltage to generate a comparison value. The controller presets the digital control input, prompts the DAC to sample the input voltage onto the sample node, resets the digital control input, and performs a conversion by successively adjusting the digital control input based on the comparison value to determine a digital output. A preset value is subtracted from the digital output to provide an adjusted digital output. A sample predictor predicts the next sample to determine the preset value used to adjust the sample node within a full scale range after DAC reset.

公开(公告)号：US10938401B1

公开(公告)日：2021-03-02

申请号：US16693557

申请日：2019-11-25

Applicant: NXP B.V.

Inventor： Erik Olieman ,  Alphons Litjes ,  Ibrahim Candan

IPC: H03M1/00 ,  H03M1/46 ,  H03M1/42 ,  H03M1/80 ,  H03M1/78 ,  H03M1/68

Abstract: Embodiments of an analog-to-digital converter (ADC), resistive digital-to-analog converter (DAC) circuits, and methods of operating an ADC are disclosed. In an embodiment, an analog-to-digital converter includes a DAC unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC, a comparator configured to compare the first voltage with a second voltage to generate a comparison output, and a logic circuit configured to generate the digital code, to control the DAC unit based on the comparison output, and to output the digital code as a digital output of the ADC. The DAC unit includes a capacitive DAC and multiple resistive DACs. Each of the resistive DACs is connected to the first voltage through a respective capacitor.

公开(公告)号：US11791832B2

公开(公告)日：2023-10-17

申请号：US17577501

申请日：2022-01-18

Applicant: NXP B.V.

Inventor： Erik Olieman ,  Rene Verlinden ,  Helmut Kranabenter

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO− signals, and outputs a second controlled LO signal output to a sense circuit.

公开(公告)号：US20250119118A1

公开(公告)日：2025-04-10

申请号：US18484708

申请日：2023-10-11

Applicant: NXP B.V.

Inventor： Rajesh Prabhakar Shamala ,  Stephane Damien Thuriés ,  Achal Venkatesh ,  Erik Olieman

IPC: H03H11/04

Abstract: A device includes a filter circuit having both a transformer and a notch filter. The notch filter is formed via capacitive cross-coupling of windings of the transformer. The transformer includes a first winding with an input terminal and an output terminal and a second winding with an input terminal and an output terminal. The notch filter is formed by coupling a first capacitor between the input terminal of the first winding and the output terminal of the second winding, and by coupling a second capacitor between the output terminal of the first winding and the input terminal of the second winding.

公开(公告)号：US10958282B2

公开(公告)日：2021-03-23

申请号：US16813823

申请日：2020-03-10

Applicant: NXP B.V.

Inventor： Erik Olieman ,  Alphons Litjes ,  Leon van der Dussen

IPC: H03M1/12 ,  H03M1/46

Abstract: A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-terminal.

公开(公告)号：US20200313689A1

公开(公告)日：2020-10-01

申请号：US16813823

申请日：2020-03-10

Applicant: NXP B.V.

Inventor： Erik Olieman ,  Alphons Litjes ,  Leon van der Dussen

IPC: H03M1/46 ,  H03M1/12

Abstract: A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-terminal.