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公开(公告)号：US20160043703A1
公开(公告)日：2016-02-11
申请号：US14798933
申请日：2015-07-14
Applicant: NXP B.V.
Inventor： Jean-Robert Tourret
IPC: H03H17/08
CPC classification number: H03H17/08 , H03D13/00 , H05B6/686 , H05B6/705 , H05B6/72 , Y02B40/143 , Y02B40/146
Abstract: An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.
Abstract translation: 一种用于检测施加到RF信号的相移量的RF电路和方法。 包括RF电路的RF加热装置。 RF电路包括一个移相器，可操作以将相移施加到参考信号以产生相移基准信号。 RF电路还包括可用于检测相移RF信号和相移参考信号之间的相位差的相位检测器。 相位检测器在相移RF信号的频率处具有减小的输入范围。 RF电路还包括控制器，其可操作以控制移相器设置相移参考信号的相位，使得相移RF信号和相移参考信号之间的相位差落入相位检测器的减小的输入范围内 。
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公开(公告)号：US20250138564A1
公开(公告)日：2025-05-01
申请号：US18914694
申请日：2024-10-14
Applicant: NXP B.V.
Inventor： Vincent Geffroy , Jean-Robert Tourret , Franck Goussin , Frederic Darthenay
Abstract: A voltage regulator utilizes an external pass transistor coupled between a supply voltage node and a regulated node. The voltage regulator includes an internal pass transistor that is coupled between the supply voltage node and the regulated node. A two-tap voltage divider between the regulated node and a ground node provides two feedback voltages. A first control loop that controls the external pass transistor receives the first feedback voltage and a second control loop that controls the internal pass transistor receives the second feedback voltage. At startup the control loops run concurrently but the first control loop is prioritized to reduce load current provided by the internal pass transistor at the end of startup. The voltage difference between the first and second feedback voltages ensures prioritization of the first control loop and the external pass transistor supplies most or all of the load current.
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公开(公告)号：US20240113709A1
公开(公告)日：2024-04-04
申请号：US18467053
申请日：2023-09-14
Applicant: NXP B.V.
Inventor： Jean-Robert Tourret
IPC: H03K17/687 , H03K19/0175
CPC classification number: H03K17/6871 , H03K19/017509 , H02M3/155
Abstract: A bias circuit for generating a virtual reference voltage is described. The bias circuit may bias a switching device configured to switch a switching device output between a first and second supply voltage. The bias circuit includes a bias stage coupled between the first supply voltage rail and the second supply voltage rail. The bias stage has a bias stage output configured to output a virtual reference voltage value having a value between the first and second supply voltage. The bias circuit further includes a voltage follower coupled to the bias stage. The voltage follower is configured to output the virtual reference voltage. The bias circuit further includes a first charge pump coupled to the voltage follower output; and at least one of a second charge pump coupled to the bias stage voltage output, and a switchable buffer coupled to the bias stage voltage output and the voltage follower output.
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公开(公告)号：US20240113612A1
公开(公告)日：2024-04-04
申请号：US18467030
申请日：2023-09-14
Applicant: NXP B.V.
Inventor： Jean-Robert Tourret
CPC classification number: H02M1/0045 , H02M1/08 , H02M3/07
Abstract: A low drop-out (LDO) regulator, includes an NMOS transistor having one of a source and drain terminal configured to be coupled to a voltage supply and the other of the source and drain terminal coupled to the low drop out voltage regulator output. A gate driver for the LDO regulator includes a boost converter having a boost converter input configured to be coupled to a boost converter reference voltage, a boost converter output configured to output a boosted voltage greater than the boost converter reference voltage and the voltage supply; and a boost converter clock input configured to receive a clock signal. The gate driver further includes a notch filter having a notch filter input coupled to the boost converter output and a notch filter output coupled to the gate driver output.
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公开(公告)号：US20240393910A1
公开(公告)日：2024-11-28
申请号：US18664150
申请日：2024-05-14
Applicant: NXP B.V.
Inventor： Frederic Darthenay , Jean-Robert Tourret , Franck Goussin , Vincent Geffroy
Abstract: A touch screen is disclosed having a length and a height, and comprising interspaced and galvanically isolated first and second arrays of touch pads; wherein the first array of touch pads comprises a plurality of first strings of series-connected touch pads, each first string forming a drive line and extending in a first general direction; wherein the second array of touch pads comprises a plurality of second strings of series-connected touch pads, each second string forming a read line and extending in a second general direction, different to said first general direction; wherein the first general direction and the second general direction are each different from the length direction; and wherein the touch screen is configured for capacitive-based sensing which may be based on a change in a mutual capacitance between individual ones of the drive lines and individual ones of the read lines.
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Patent Agency Ranking
公开(公告)号：US20240126320A1
公开(公告)日：2024-04-18
申请号：US18484997
申请日：2023-10-11
Applicant: NXP B.V.
Inventor： Jean-Robert Tourret
IPC: G06F1/06 , H03K3/037 , H03K5/00 , H03K5/13 , H03K5/1534
CPC classification number: G06F1/06 , H03K3/037 , H03K5/00006 , H03K5/13 , H03K5/1534 , H03K2005/00058
Abstract: A plurality of chained clock dividers provides a plurality of generated clocks generated from a root clock. Each clock divider provides a generated clock having a lower frequency that its corresponding input clock and which transitions at falling edges of its corresponding input clock. Clock gating circuitry selectively gates the generated clocks based on a clock ready signal and provides the generated clocks as a corresponding plurality of safe clocks when the clock ready indicator indicates the generated clocks are ready. A delay circuit has an inverted clock input configured to receive a final generated clock. The delay circuit provides a trigger output in response to a falling edge of the final generated clock. A set of synchronization flip flops receives a clock enable signal and the trigger output and provides the clock ready indicator based on the clock enable signal and the trigger output.
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公开(公告)号：US20160043728A1
公开(公告)日：2016-02-11
申请号：US14821481
申请日：2015-08-07
Applicant: NXP B.V.
Inventor： Jean-Robert Tourret
CPC classification number: H03L7/235 , H03L7/07 , H03L7/099 , H03L7/18 , H03L7/22 , H03L7/23 , H05B6/00
Abstract: An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronisation signal divider for distributing a synchronisation signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronisation signal divider.
Abstract translation: 一种用于提供相位相干信号的RF电路，包括RF电路的RF加热装置和用于在RF电路中提供相位相干信号的方法。 RF电路具有包括N分相锁相环的第一频率合成器和包括整数N个锁相环的第二频率合成器。 第一频率合成器的输出经由用于将来自第一频率合成器的同步信号分配给第二频率合成器的同步信号分频器连接到第二频率合成器的整数N锁相环的相位频率检测器。 第二频率合成器的整数N锁相环包括与同步信号分频器相同模数的分频器。
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公开(公告)号：US20250036238A1
公开(公告)日：2025-01-30
申请号：US18764690
申请日：2024-07-05
Applicant: NXP B.V.
Inventor： Jean-Robert Tourret , Franck Goussin , Frederic Darthenay , Vincent Geffroy
Abstract: A method for display noise canceling in a touch sensing system includes measuring a first feedback voltage of a feedback node resistively coupled to a line voltage of a capacitive touch panel, the line voltage formed by a continuous wave output of an amplifier responsive to a reference voltage difference between the first feedback voltage and a reference voltage. A second feedback voltage is clamped to a first upper voltage threshold in response to a first voltage difference between the first feedback voltage and the reference voltage being greater than the first upper voltage threshold. The second feedback voltage is clamped to a first lower voltage threshold in response to the first voltage difference being less than the first lower voltage threshold.
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9.发明公开公开(公告)号：US20240302918A1
公开(公告)日：2024-09-12
申请号：US18587195
申请日：2024-02-26
Applicant: NXP B.V.
Inventor： Franck Goussin , Frederic Darthenay , Jean-Robert Tourret , Vincent Geffroy
CPC classification number: G06F3/04166 , G06F3/0446
Abstract: A touch panel system that includes drivers for providing detection signals on a first plurality of electrodes of a touch panel where each detection signal includes one or more frequency signal components with each frequency signal component having a frequency and a phase offset. The detection signals includes at least three phase offsets for at least one frequency of the frequency signal components. Each detection signal has a unique frequency-phase offset combination of the one or more frequency signal components. The unique combinations allow for the determination of a touch at specific locations on the panel by sensing signals on a second set of electrodes.
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公开(公告)号：US09331678B2
公开(公告)日：2016-05-03
申请号：US14077912
申请日：2013-11-12
Applicant: NXP B.V.
Inventor： Jean-Robert Tourret
CPC classification number: H03K3/037 , H03B19/00 , H03L7/0812
Abstract: A local oscillator signal generation circuit for a frequency divider circuit is disclosed. The local oscillator signal generation circuit includes a delay device adapted to delay a data signal according to a control signal, a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided to its clock input terminal and a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and to generate a control signal based on the first and second partially overlapping pulse windows and the reference clocking signal. The control signal is provided to the delay device to control the amount by which the data signal is delayed so that the data signal is stable when it is sampled by the data flip-flop. A local oscillator signal is derived from the output of the data flip-flop.
Abstract translation: 公开了一种用于分频器电路的本地振荡器信号产生电路。 本地振荡器信号产生电路包括适于根据控制信号延迟数据信号的延迟装置，具有提供给其数据输入端的延迟数据信号的数据触发器和提供给其时钟输入端的参考时钟信号，以及 控制电路，适于从延迟的数据信号产生第一和第二部分重叠的脉冲窗口，并且基于第一和第二部分重叠的脉冲窗口和参考计时信号产生控制信号。 控制信号被提供给延迟装置以控制数据信号被延迟的量，使得数据信号在被数据触发器采样时是稳定的。 本地振荡器信号从数据触发器的输出导出。
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