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    SEMICONDUCTOR HETEROJUNCTION DEVICE
    1.
    发明申请
    SEMICONDUCTOR HETEROJUNCTION DEVICE 有权
    半导体异质结器件

    公开(公告)号：US20150228774A1

    公开(公告)日：2015-08-13

    申请号：US14613182

    申请日：2015-02-03

    Applicant: NXP B.V.

    Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Godefridus Adrianus Maria Hurkx ,  Stephan Bastiaan Simon Heil ,  Michael Antoine Armand In 't Zandt

    IPC: H01L29/778 ,  H01L29/872 ,  H01L29/205 ,  H01L23/31 ,  H01L29/20 ,  H01L29/201

    CPC classification number: H01L29/7787 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/405 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A heterojunction semiconductor device (200) comprising a substrate (202) and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (204), which comprises a first semiconductor disposed on top of the substrate, and a second layer (206), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (220) forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer (208) disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal (210) electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal (212) electrically coupled to a second area of the heterojunction semiconductor device. The second terminal (212) is electrically coupled to the semiconductor passivation layer such that electric charge can flow into the second terminal (212) from the semiconductor passivation layer (208).

    Abstract translation: 一种异质结半导体器件（200），包括衬底（202）和设置在衬底上的多层结构。 所述多层结构包括第一层（204），其包括设置在所述衬底顶部上的第一半导体和第二层（206），所述第二层（206）包括设置在所述第一层顶部上以限定所述第一层 层和第二层。 第二半导体与第一半导体不同，使得邻近界面形成二维电子气（220）。 多层结构还包括钝化层，其包括设置在第二层顶部上的半导体钝化层（208）。 异质结半导体器件还包括电耦合到异质结半导体器件的第一区域的第一端子（210） 以及电耦合到异质结半导体器件的第二区域的第二端子（212）。 第二端子（212）电耦合到半导体钝化层，使得电荷可以从半导体钝化层（208）流入第二端子（212）。

    Semiconductor heterojunction device
    2.
    发明授权
    Semiconductor heterojunction device 有权
    半导体异质结装置

    公开(公告)号：US09391187B2

    公开(公告)日：2016-07-12

    申请号：US14723247

    申请日：2015-05-27

    Applicant: NXP B.V.

    Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Stephan Bastiaan Simon Heil ,  Jan Sonsky

    IPC: H01L29/20 ,  H01L29/36 ,  H01L29/778 ,  H01L29/205 ,  H01L29/32 ,  H01L29/417 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/207

    CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/66143 ,  H01L29/7786 ,  H01L29/872

    Abstract: In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.

    Abstract translation: 在示例性实施例中，异质结装置包括衬底，设置在衬底上的多层结构。 所述多层结构具有设置在所述基板顶部的具有第一半导体的第一层; 第二层具有第二半导体设置在第一层的顶部，限定它们之间的界面。 第二半导体与第一半导体不同，使得2D电子气体与界面相邻形成。 第一端子耦合到第一和第二层之间的界面的第一区域，并且第二端子耦合到第一层和第二层之间的界面的第二区域; 导电通道包括具有比第一层的另一区域更高的缺陷密度的第一层的金属或区域。 通道连接第二端子和第一层的区域，使得电荷在它们之间流动。

    Semiconductor heterojunction device
    3.
    发明授权
    Semiconductor heterojunction device 有权
    半导体异质结装置

    公开(公告)号：US09385226B2

    公开(公告)日：2016-07-05

    申请号：US14613182

    申请日：2015-02-03

    Applicant: NXP B.V.

    Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Godefridus Adrianus Maria Hurkx ,  Stephan Bastiaan Simon Heil ,  Michael Antoine Armand in 't Zandt

    IPC: H01L29/15 ,  H01L29/778 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L23/31 ,  H01L29/872 ,  H01L29/267 ,  H01L29/40

    CPC classification number: H01L29/7787 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/405 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A heterojunction semiconductor device (200) comprising a substrate (202) and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (204), which comprises a first semiconductor disposed on top of the substrate, and a second layer (206), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (220) forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer (208) disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal (210) electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal (212) electrically coupled to a second area of the heterojunction semiconductor device. The second terminal (212) is electrically coupled to the semiconductor passivation layer such that electric charge can flow into the second terminal (212) from the semiconductor passivation layer (208).

    Abstract translation: 一种异质结半导体器件（200），包括衬底（202）和设置在衬底上的多层结构。 所述多层结构包括第一层（204），其包括设置在所述衬底顶部上的第一半导体和第二层（206），所述第二层（206）包括设置在所述第一层顶部上以限定所述第一层 层和第二层。 第二半导体与第一半导体不同，使得邻近界面形成二维电子气（220）。 多层结构还包括钝化层，其包括设置在第二层顶部上的半导体钝化层（208）。 异质结半导体器件还包括电耦合到异质结半导体器件的第一区域的第一端子（210） 以及电耦合到异质结半导体器件的第二区域的第二端子（212）。 第二端子（212）电耦合到半导体钝化层，使得电荷可以从半导体钝化层（208）流入第二端子（212）。

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