公开(公告)号：US08962461B2

公开(公告)日：2015-02-24

申请号：US14108042

申请日：2013-12-16

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Stephan Heil ,  Jan Sonsky

IPC: H01L21/28 ,  H01L21/44 ,  H01L29/47 ,  H01L29/40 ,  H01L29/778 ,  H01L29/872 ,  H01L23/31 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/475 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.

Abstract translation: 与示例性实施例一致，GaN异质结结构具有三层电介质结构。 栅电极的最下部和中部一起限定栅极脚，并且这与两个电介质层相关联。 较薄的第一介电层与栅极底部的栅极边缘相邻。 第二电介质层对应于常规结构中的层，并且与栅极脚的主要部分平齐。

公开(公告)号：US09349819B2

公开(公告)日：2016-05-24

申请号：US14714927

申请日：2015-05-18

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Stephen John Sque ,  Andreas Bernardus Maria Jansman ,  Markus Mueller ,  Stephan Heil ,  Tim Boettcher

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/47 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/872 ,  H01L29/40

CPC classification number: H01L29/475 ,  H01L21/02362 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/417 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/872

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Abstract translation: 公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分 用于局部增加肖特基电极的肖特基势垒。 还公开了制造这种半导体器件的方法。

公开(公告)号：US20140167064A1

公开(公告)日：2014-06-19

申请号：US14108042

申请日：2013-12-16

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Stephan Heil ,  Jan Sonsky

IPC: H01L29/47 ,  H01L29/872 ,  H01L29/778 ,  H01L29/40

CPC classification number: H01L29/475 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A GaN hetereojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectric layer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.

Abstract translation: GaN半导体结构具有三层电介质结构。 栅电极的最下部和中部一起限定栅极脚，并且这与两个电介质层相关联。 较薄的第一介电层与栅极底部的栅极边缘相邻。 第二电介质层对应于传统结构中的层，并且与栅极脚的主要部分平齐。

公开(公告)号：US20170170089A1

公开(公告)日：2017-06-15

申请号：US15356519

申请日：2016-11-18

Applicant: NXP B.V.

Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Mark Andrzej Gajda ,  Jan Sonsky

IPC: H01L23/31 ,  H01L29/205 ,  H01L21/56 ,  H01L29/872 ,  H01L23/29 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L23/3171 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials. The different passivation materials may be compositions of silicon nitride that include different proportions of silicon

公开(公告)号：US09391187B2

公开(公告)日：2016-07-12

申请号：US14723247

申请日：2015-05-27

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Stephan Bastiaan Simon Heil ,  Jan Sonsky

IPC: H01L29/20 ,  H01L29/36 ,  H01L29/778 ,  H01L29/205 ,  H01L29/32 ,  H01L29/417 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/207

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/66143 ,  H01L29/7786 ,  H01L29/872

Abstract: In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.

Abstract translation: 在示例性实施例中，异质结装置包括衬底，设置在衬底上的多层结构。 所述多层结构具有设置在所述基板顶部的具有第一半导体的第一层; 第二层具有第二半导体设置在第一层的顶部，限定它们之间的界面。 第二半导体与第一半导体不同，使得2D电子气体与界面相邻形成。 第一端子耦合到第一和第二层之间的界面的第一区域，并且第二端子耦合到第一层和第二层之间的界面的第二区域; 导电通道包括具有比第一层的另一区域更高的缺陷密度的第一层的金属或区域。 通道连接第二端子和第一层的区域，使得电荷在它们之间流动。

公开(公告)号：US09385226B2

公开(公告)日：2016-07-05

申请号：US14613182

申请日：2015-02-03

Applicant: NXP B.V.

Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Godefridus Adrianus Maria Hurkx ,  Stephan Bastiaan Simon Heil ,  Michael Antoine Armand in 't Zandt

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L23/31 ,  H01L29/872 ,  H01L29/267 ,  H01L29/40

CPC classification number: H01L29/7787 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/405 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heterojunction semiconductor device (200) comprising a substrate (202) and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (204), which comprises a first semiconductor disposed on top of the substrate, and a second layer (206), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (220) forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer (208) disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal (210) electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal (212) electrically coupled to a second area of the heterojunction semiconductor device. The second terminal (212) is electrically coupled to the semiconductor passivation layer such that electric charge can flow into the second terminal (212) from the semiconductor passivation layer (208).

Abstract translation: 一种异质结半导体器件（200），包括衬底（202）和设置在衬底上的多层结构。 所述多层结构包括第一层（204），其包括设置在所述衬底顶部上的第一半导体和第二层（206），所述第二层（206）包括设置在所述第一层顶部上以限定所述第一层 层和第二层。 第二半导体与第一半导体不同，使得邻近界面形成二维电子气（220）。 多层结构还包括钝化层，其包括设置在第二层顶部上的半导体钝化层（208）。 异质结半导体器件还包括电耦合到异质结半导体器件的第一区域的第一端子（210） 以及电耦合到异质结半导体器件的第二区域的第二端子（212）。 第二端子（212）电耦合到半导体钝化层，使得电荷可以从半导体钝化层（208）流入第二端子（212）。

公开(公告)号：US20170154988A1

公开(公告)日：2017-06-01

申请号：US15356509

申请日：2016-11-18

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Jeroen Antoon Croon

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/872 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

Abstract: A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.

公开(公告)号：US20160020296A1

公开(公告)日：2016-01-21

申请号：US14714927

申请日：2015-05-18

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Stephen John Sque ,  Andreas Bernardus Maria Jansman ,  Markus Mueller ,  Stephan Heil ,  Tim Boettcher

IPC: H01L29/47 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/475 ,  H01L21/02362 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/417 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/872

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

公开(公告)号：US20150228774A1

公开(公告)日：2015-08-13

申请号：US14613182

申请日：2015-02-03

Applicant: NXP B.V.

Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Godefridus Adrianus Maria Hurkx ,  Stephan Bastiaan Simon Heil ,  Michael Antoine Armand In 't Zandt

IPC: H01L29/778 ,  H01L29/872 ,  H01L29/205 ,  H01L23/31 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/7787 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/405 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heterojunction semiconductor device (200) comprising a substrate (202) and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (204), which comprises a first semiconductor disposed on top of the substrate, and a second layer (206), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (220) forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer (208) disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal (210) electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal (212) electrically coupled to a second area of the heterojunction semiconductor device. The second terminal (212) is electrically coupled to the semiconductor passivation layer such that electric charge can flow into the second terminal (212) from the semiconductor passivation layer (208).

Abstract translation: 一种异质结半导体器件（200），包括衬底（202）和设置在衬底上的多层结构。 所述多层结构包括第一层（204），其包括设置在所述衬底顶部上的第一半导体和第二层（206），所述第二层（206）包括设置在所述第一层顶部上以限定所述第一层 层和第二层。 第二半导体与第一半导体不同，使得邻近界面形成二维电子气（220）。 多层结构还包括钝化层，其包括设置在第二层顶部上的半导体钝化层（208）。 异质结半导体器件还包括电耦合到异质结半导体器件的第一区域的第一端子（210） 以及电耦合到异质结半导体器件的第二区域的第二端子（212）。 第二端子（212）电耦合到半导体钝化层，使得电荷可以从半导体钝化层（208）流入第二端子（212）。