公开(公告)号：US06943373B2

公开(公告)日：2005-09-13

申请号：US10693987

申请日：2003-10-28

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： G11C11/41 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/10 ,  H01L29/72

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US20050253143A1

公开(公告)日：2005-11-17

申请号：US11168872

申请日：2005-06-29

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： G11C11/41 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/10

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

摘要翻译： 本发明提供一种包括多个字线，多个位线以及多个静态存储单元的半导体存储器件，每个静态存储器单元具有第一，第二，第三，第四，第五和第六和第六晶体管。 尽管第一，第二，第三和第四晶体管的每个通道与半导体存储器件的衬底垂直地形成。 形成第五晶体管和第六晶体管的源极或漏极的半导体区域形成与衬底相反的PN结。 根据本发明的另一方面，本发明的SRAM器件具有多个SRAM单元，其中至少一个是在衬底上包括至少四个垂直晶体管的垂直SRAM单元，并且每个垂直晶体管包括源极， 排水管和其间的通道在以大于零度的角度穿入衬底表面的一个对准线对中。

公开(公告)号：US07098478B2

公开(公告)日：2006-08-29

申请号：US11168872

申请日：2005-06-29

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L29/72

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US06670642B2

公开(公告)日：2003-12-30

申请号：US10051188

申请日：2002-01-22

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US06538945B2

公开(公告)日：2003-03-25

申请号：US10050561

申请日：2002-01-18

申请人： Riichiro Takemura ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Ryo Nagai ,  Norikatsu Takaura ,  Tomonori Sekiguchi ,  Shinichiro Kimura

发明人： Riichiro Takemura ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Ryo Nagai ,  Norikatsu Takaura ,  Tomonori Sekiguchi ,  Shinichiro Kimura

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10897

摘要： Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.

公开(公告)号：US06809364B2

公开(公告)日：2004-10-26

申请号：US10630695

申请日：2003-07-31

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

公开(公告)号：US06621110B1

公开(公告)日：2003-09-16

申请号：US09592648

申请日：2000-06-13

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

摘要翻译： 开放位线结构的DRAM具有小于折叠位线结构的DRAM的单元面积，并且易受噪声影响。 开放位线结构的常规DRAM具有大的位线电容，并且易于噪声或具有大的单元面积。 已经没有开放位线结构的DRAM具有小的位线电容，不能被噪声感知并且具有小的单元面积。 本发明形成与位线不对齐的电容器下电极插孔，以减少位线电容。 位线形成为小的宽度，电容器下电极插头从与位线相对应的位置的位置脱位，并且触点形成为减小的直径，以避免增加电池面积。 因此，提供了耐噪声且具有小单元面积的开放位线结构的半导体存储装置。

公开(公告)号：US20120249180A1

公开(公告)日：2012-10-04

申请号：US13429056

申请日：2012-03-23

申请人： Takamasa SUZUKI ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Takamasa SUZUKI ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H03K19/0175

CPC分类号： H03K3/35613

摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.

摘要翻译： 本文公开了一种可用于电平移位电路的装置。 该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路， 第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管 电源线，使第五晶体管不导通以使第一反相器停用;以及控制电路，被配置为在第一反相器停用期间防止输出端子进入电浮动状态。

公开(公告)号：US20110176379A1

公开(公告)日：2011-07-21

申请号：US13008408

申请日：2011-01-18

申请人： Shinichi TAKAYAMA ,  Akira Kotabe ,  Kazuo Ono ,  Tomonori Sekiguchi ,  Yoshimitsu Yanagawa ,  Riichiro Takemura

发明人： Shinichi TAKAYAMA ,  Akira Kotabe ,  Kazuo Ono ,  Tomonori Sekiguchi ,  Yoshimitsu Yanagawa ,  Riichiro Takemura

IPC分类号： G11C7/06

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.

摘要翻译： 半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。 写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位 在第二位线的数据写入时的第二本地数据线。

公开(公告)号：US20110079858A1

公开(公告)日：2011-04-07

申请号：US12967728

申请日：2010-12-14

申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

IPC分类号： H01L27/108

CPC分类号： G11C11/4091 ,  H01L27/10897

摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

摘要翻译： 具有高集成度，低功耗和高操作速度的半导体存储器件。 存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。 构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。 具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。 数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。