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    Semiconductor memory device using vertical-channel transistors
    2.
    发明申请
    Semiconductor memory device using vertical-channel transistors 失效
    半导体存储器件采用垂直沟道晶体管

    公开(公告)号：US20050253143A1

    公开(公告)日：2005-11-17

    申请号：US11168872

    申请日：2005-06-29

    申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

    发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

    IPC分类号： G11C11/41 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/10

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

    摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

    摘要翻译： 本发明提供一种包括多个字线，多个位线以及多个静态存储单元的半导体存储器件，每个静态存储器单元具有第一，第二，第三，第四，第五和第六和第六晶体管。 尽管第一，第二，第三和第四晶体管的每个通道与半导体存储器件的衬底垂直地形成。 形成第五晶体管和第六晶体管的源极或漏极的半导体区域形成与衬底相反的PN结。 根据本发明的另一方面，本发明的SRAM器件具有多个SRAM单元，其中至少一个是在衬底上包括至少四个垂直晶体管的垂直SRAM单元，并且每个垂直晶体管包括源极， 排水管和其间的通道在以大于零度的角度穿入衬底表面的一个对准线对中。

    Semiconductor integrated circuit device
    7.
    发明申请
    Semiconductor integrated circuit device 审中-公开
    半导体集成电路器件

    公开(公告)号：US20050035428A1

    公开(公告)日：2005-02-17

    申请号：US10946000

    申请日：2004-09-22

    申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

    发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

    IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L27/105 ,  H01L27/10897

    摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

    摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有效区域nwp1和nw1之间的宽度为L4，则有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090014770A1

    公开(公告)日：2009-01-15

    申请号：US12169789

    申请日：2008-07-09

    申请人： Motoyasu Terao ,  Hideyuki Matsuoka ,  Naohiko Irie ,  Yoshitaka Sasago ,  Riichiro Takemura ,  Norikatsu Takaura

    发明人： Motoyasu Terao ,  Hideyuki Matsuoka ,  Naohiko Irie ,  Yoshitaka Sasago ,  Riichiro Takemura ,  Norikatsu Takaura

    IPC分类号： H01L29/00

    CPC分类号： H01L45/145 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2213/11 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

    摘要： A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.

    摘要翻译： 通过采用能够高精度地控制固体电解质中的离子的运动的装置结构，通过提高具有记录或切换功能的半导体器件的性能，可以以低成本实现多层次三维结构的高集成度的技术。 器件的半导体元件如下形成; 分别在垂直（z轴）方向上分开设置的一对电极之间分别沉积两层或更多层，然后在这些电极之间施加脉冲电压以形成导电路径。 路径的电阻值根据信息信号而变化。 此外，在导电路径的中间部分形成区域。 该区域用于累积改善路径的导电性的分量，从而使电阻值（速率）能够当前响应于信息信号。 更优选地，电极也应至少形成在x轴方向或y轴方向上，以向电极施加控制电压。

    Semiconductor device with ion movement control
    10.
    发明授权
    Semiconductor device with ion movement control 有权
    半导体器件具有离子运动控制

    公开(公告)号：US07829930B2

    公开(公告)日：2010-11-09

    申请号：US12169789

    申请日：2008-07-09

    申请人： Motoyasu Terao ,  Hideyuki Matsuoka ,  Naohiko Irie ,  Yoshitaka Sasago ,  Riichiro Takemura ,  Norikatsu Takaura

    发明人： Motoyasu Terao ,  Hideyuki Matsuoka ,  Naohiko Irie ,  Yoshitaka Sasago ,  Riichiro Takemura ,  Norikatsu Takaura

    IPC分类号： H01L27/108

    CPC分类号： H01L45/145 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2213/11 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

    摘要： A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.

    摘要翻译： 通过采用能够高精度地控制固体电解质中的离子的运动的装置结构，通过提高具有记录或切换功能的半导体器件的性能，可以以低成本实现多层次三维结构的高集成度的技术。 器件的半导体元件如下形成; 分别在垂直（z轴）方向上分开设置的一对电极之间分别沉积两层或更多层，然后在这些电极之间施加脉冲电压以形成导电路径。 路径的电阻值根据信息信号而变化。 此外，在导电路径的中间部分形成区域。 该区域用于累积改善路径的导电性的分量，从而使电阻值（速率）能够当前响应于信息信号。 更优选地，电极也应至少形成在x轴方向或y轴方向上，以向电极施加控制电压。