公开(公告)号：US4930105A

公开(公告)日：1990-05-29

申请号：US178609

申请日：1988-04-07

申请人： Osamu Matsumoto ,  Tadashi Maruyama ,  Hiroyoshi Murata ,  Isao Abe ,  Tomohisa Shigematsu ,  Kazuyoshi Shinada ,  Yasoji Suzuki ,  Ichiro Kobayashi

发明人： Osamu Matsumoto ,  Tadashi Maruyama ,  Hiroyoshi Murata ,  Isao Abe ,  Tomohisa Shigematsu ,  Kazuyoshi Shinada ,  Yasoji Suzuki ,  Ichiro Kobayashi

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/0425

摘要： A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

公开(公告)号：US4988894A

公开(公告)日：1991-01-29

申请号：US365739

申请日：1989-06-14

申请人： Akira Takiba ,  Hiroyoshi Murata ,  Yasoji Suzuki ,  Isao Abe

发明人： Akira Takiba ,  Hiroyoshi Murata ,  Yasoji Suzuki ,  Isao Abe

IPC分类号： H03K17/10 ,  H03K17/693

CPC分类号： H03K17/102 ,  H03K17/693

摘要： A power supply switching circuit includes first to third MOS transistors (P1, P2 and P3) connected in series between a high-potential source and a standard-potential source. The circuit performs a switching operation using a standard-potential and at least one potential which is different from the standard-poential, and outputs plural power supply potentials. The third MOS transistor (P3) is inserted between the first and second MOS transistors (P1 and P2). The back gate of the third transistor (P3) is connected to an output terminal (OUT1) formed between the second transistor (P2) and the third transistor (P3) and prevents the formation of a current path via turned-off transistor (P1) due to the action of a parasitic diode in the first and second transistors caused by potential fluctuations.

公开(公告)号：US6020869A

公开(公告)日：2000-02-01

申请号：US841389

申请日：1997-04-30

申请人： Itsuo Sasaki ,  Yasoji Suzuki ,  Hirofumi Kato ,  Isao Arita ,  Toshio Yanagisawa ,  Kazuyoshi Yamamoto ,  Hiroyoshi Murata ,  Hiroyuki Hamagawa

发明人： Itsuo Sasaki ,  Yasoji Suzuki ,  Hirofumi Kato ,  Isao Arita ,  Toshio Yanagisawa ,  Kazuyoshi Yamamoto ,  Hiroyoshi Murata ,  Hiroyuki Hamagawa

IPC分类号： G09G3/20 ,  G09G3/36 ,  G09G3/28 ,  G09G3/30 ,  G09G5/10

CPC分类号： G09G3/3648 ,  G09G2310/027 ,  G09G3/2007 ,  G09G3/2018

摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

公开(公告)号：US06459416B1

公开(公告)日：2002-10-01

申请号：US09265795

申请日：1999-03-10

申请人： Itsuo Sasaki ,  Yasoji Suzuki ,  Hirofumi Kato ,  Isao Arita ,  Toshio Yanagisawa ,  Kazuyoshi Yamamoto ,  Hiroyoshi Murata ,  Hiroyuki Hamagawa

发明人： Itsuo Sasaki ,  Yasoji Suzuki ,  Hirofumi Kato ,  Isao Arita ,  Toshio Yanagisawa ,  Kazuyoshi Yamamoto ,  Hiroyoshi Murata ,  Hiroyuki Hamagawa

IPC分类号： G09G328

CPC分类号： G09G3/3648 ,  G09G3/2007 ,  G09G3/2018 ,  G09G2310/027

摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

摘要翻译： 通过使用少量电压，设计用于显示无闪烁等的多灰度级图像的多灰度级显示器。 显示器包括：第一灰度级图形生成电路311，用于产生在m个帧周期期间获取灰度级的第一灰度级图形;第二灰度级图形生成电路321，用于生成获取另一灰度级图案的第二灰度级图案 在n个帧周期（n是大于m的正整数）的灰度级，以及根据来自第一灰度级图形生成电路311或第二灰度级图形生成电路311的输出，选择并输出预设电压之一的选择电路341 当输入的多灰度级显示数据对应于第一灰度级图案或第二灰度级图案的灰度级时，灰度级图形产生电路321。

公开(公告)号：US20090122024A1

公开(公告)日：2009-05-14

申请号：US12260656

申请日：2008-10-29

申请人： Takashi NAKAMURA ,  Takayuki Imai ,  Hirotaka Hayashi ,  Hiroki Nakamura ,  Masayoshi Fuchi ,  Masahiro Tada ,  Hiroyoshi Murata

发明人： Takashi NAKAMURA ,  Takayuki Imai ,  Hirotaka Hayashi ,  Hiroki Nakamura ,  Masayoshi Fuchi ,  Masahiro Tada ,  Hiroyoshi Murata

IPC分类号： G06F3/041

CPC分类号： G06F3/042 ,  G06F3/0416 ,  G06F3/044

摘要： In a display device, an object approaching a display unit is detected by referring to an image picked up by the display unit. An alternating current drive circuit drives an alternating current signal to the display unit, so that a detection circuit detects an amplitude change or a phase shift. Alternatively, a liquid crystal panel is vibrated at a predetermined frequency, so that the strength of the frequency of the vibration sound is detected. This makes it possible to more accurately detect the timing when the object touches the display unit.

摘要翻译： 在显示装置中，通过参照由显示单元拾取的图像来检测接近显示单元的对象。 交流驱动电路将交流信号驱动到显示单元，使得检测电路检测振幅​​变化或相移。 或者，液晶面板以预定频率振动，从而检测振动声音的频率的强度。 这使得可以更精确地检测对象接触显示单元时的定时。

公开(公告)号：US6144355A

公开(公告)日：2000-11-07

申请号：US733716

申请日：1996-10-16

申请人： Hiroyoshi Murata ,  Hirofumi Kato ,  Kohei Kinoshita

发明人： Hiroyoshi Murata ,  Hirofumi Kato ,  Kohei Kinoshita

IPC分类号： G09G3/36 ,  G09G5/18

CPC分类号： G09G3/3611 ,  G09G5/18

摘要： A display device disclosed includes a liquid crystal display panel, a signal-line driver circuit responsive to image data Data and a first clock signal CK1 for generating signals supplied to signal lines, a control signal generator circuit (12) responsive to a reference clock signal for generating and issuing first clock signal CK1 and adjustment clock signals SCK, and a delay-time adjuster circuit (14) which delays the image data by a specified time interval based on a corresponding adjustment clock signal SCK from the control signal generator circuit (12) to adjust the delay time of the first clock signal CK1 as generated by the control signal generator circuit (12) with respect to the image data Data, wherein this delay-time adjuster circuit (14) is provided with phase-locked loop or PLL circuits (16) for correction of the adjustment clock signals SCK, and a PLL circuit (34) for correction of the first clock signal CK1 being supplied to the signal-line driver circuit, thereby causing the first clock signal CK1 and the image data Data to be kept exactly in phase with each other.

摘要翻译： 所公开的显示装置包括液晶显示面板，响应于图像数据Data的信号线驱动电路和用于产生提供给信号线的信号的第一时钟信号CK1，响应于参考时钟信号的控制信号发生器电路 用于产生和发出第一时钟信号CK1和调整时钟信号SCK;以及延迟时间调节器电路（14），其基于来自控制信号发生器电路（12）的相应调整时钟信号SCK将图像数据延迟指定的时间间隔 ）调整由控制信号发生器电路（12）相对于图像数据Data生成的第一时钟信号CK1的延迟时间，其中该延迟时间调整器电路（14）设置有锁相环或PLL 用于校正调整时钟信号SCK的电路（16）和用于校正被提供给信号线驱动电路的第一时钟信号CK1的PLL电路（34），从而导致 g第一时钟信号CK1和图像数据Data保持精确地相位相位。

公开(公告)号：US20050219193A1

公开(公告)日：2005-10-06

申请号：US11088899

申请日：2005-03-25

申请人： Kazutaka Nagaoka ,  Shinichi Hirota ,  Koji Shigehiro ,  Toshinori Kanuma ,  Hiroyoshi Murata

发明人： Kazutaka Nagaoka ,  Shinichi Hirota ,  Koji Shigehiro ,  Toshinori Kanuma ,  Hiroyoshi Murata

IPC分类号： G02F1/1345 ,  G02F1/133 ,  G09F9/00 ,  G09F9/35 ,  G09G3/36 ,  H01L29/786

CPC分类号： G09G3/3674 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2330/04

摘要： A liquid crystal display includes a scan line driver (12) to drive scan lines and a power source (14) to supply voltage to the scan line driver. The scan line driver and power source are formed directly on an array substrate of the liquid crystal display. The liquid crystal display also includes a signal-line-driving IC (15) mounted on the array substrate. The IC incorporates a power source (DC voltage converter (1508) and voltage stabilizer (1509)) to supply voltage to a signal line driver (analog output circuit (1504) and the like). The power source in the IC is integrated according to a low-withstanding-voltage manufacturing process. With these configurations, the liquid crystal display is compact and is manufacturable at a low cost.

摘要翻译： 液晶显示器包括驱动扫描线的扫描线驱动器（12）和向扫描线驱动器提供电压的电源（14）。 扫描线驱动器和电源直接形成在液晶显示器的阵列基板上。 液晶显示器还包括安装在阵列基板上的信号线驱动IC（15）。 IC包括电源（DC电压转换器（1508）和稳压器（1509）），以向信号线驱动器（模拟输出电路（1504）等）提供电压。 IC中的电源根据低耐压制造过程进行集成。 利用这些配置，液晶显示器是紧凑的并且可以低成本制造。

公开(公告)号：US06876348B2

公开(公告)日：2005-04-05

申请号：US10033919

申请日：2002-01-03

申请人： Hiroyoshi Murata ,  Nobuo Yamasaki ,  Masakatsu Kitani ,  Yoshihiro Aoki

发明人： Hiroyoshi Murata ,  Nobuo Yamasaki ,  Masakatsu Kitani ,  Yoshihiro Aoki

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  C09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2300/0857

摘要： With regard to a display device having an SRAM incorporated in a pixel, a technology is disclosed, which is capable of reducing manufacturing costs by simplifying a constitution of a driver. A write voltage equivalent to white or black represented by a tone level of a normal display area is converted into a write voltage corresponding to a brightest white display or a darkest black display in the pixel, and is held in the SRAM of each pixel. In the case of normal display, display is carried out with the write voltage represented by the tone level of the normal display area. In the case of static image display, display is carried out with the write voltage corresponding to the brightest white display or the darkest black display in the pixel, the write voltage being held in the SRAM. Since the normal display and the static image display can be carried out with a write voltage supplied from one driver, the constitution of the driver can be simplified.

摘要翻译： 关于具有并入像素的SRAM的显示装置，公开了通过简化驾驶员的构成能够降低制造成本的技术。 将由正常显示区域的色调等级表示的白色或黑色的写入电压转换成与像素中的最亮的白色显示或最黑色的黑色显示对应的写入电压，并保持在每个像素的SRAM中。 在正常显示的情况下，以正常显示区域的音调电平表示的写入电压进行显示。 在静态图像显示的情况下，以对应于像素中最亮的白色显示或最黑黑色显示的写入电压进行显示，写入电压保持在SRAM中。 由于可以用从一个驾驶员提供的写入电压来执行正常显示和静态图像显示，因此可以简化驾驶员的构成。

公开(公告)号：US06256003B1

公开(公告)日：2001-07-03

申请号：US09006954

申请日：1998-01-14

申请人： Kenshi Tsuchiya ,  Hirofumi Kato ,  Hiroyoshi Murata

发明人： Kenshi Tsuchiya ,  Hirofumi Kato ,  Hiroyoshi Murata

IPC分类号： G09G336

CPC分类号： G09G5/008 ,  G09G2320/02 ,  H04N5/126

摘要： A jitter correction circuit includes a delayed signal generator and an output circuit. A correction subject signal Ckd0 is derived from multiplying a horizontal synchronization signal or a reference signal Vref. The correction subject signal includes jitters. The delayed signal generator is provided with a plurality of delay elements Fd1 through Fdn which receive and delay the correction subject signal, respectively, by predetermined delay time to generate delayed signals Ckd1 through Ckdn. The output circuit outputs one of the correction subject signal Ckd0 and the delayed signals Ckd1 trough Ckdn on the condition that it has predetermined timing relationship with the reference signal Vref.

摘要翻译： 抖动校正电路包括延迟信号发生器和输出电路。 通过乘以水平同步信号或参考信号Vref导出校正对象信号Ckd0。 校正主体信号包括抖动。 延迟信号发生器设置有多个延迟元件Fd1至Fdn，它们分别接收和延迟校正对象信号预定的延迟时间以产生延迟信号Ckd1至Ckdn。 输出电路在与基准信号Vref具有预定定时关系的条件下，通过Ckdn输出校正对象信号Ckd0和延迟信号Ckd1中的一个。