公开(公告)号：US6020869A

公开(公告)日：2000-02-01

申请号：US841389

申请日：1997-04-30

申请人： Itsuo Sasaki ,  Yasoji Suzuki ,  Hirofumi Kato ,  Isao Arita ,  Toshio Yanagisawa ,  Kazuyoshi Yamamoto ,  Hiroyoshi Murata ,  Hiroyuki Hamagawa

发明人： Itsuo Sasaki ,  Yasoji Suzuki ,  Hirofumi Kato ,  Isao Arita ,  Toshio Yanagisawa ,  Kazuyoshi Yamamoto ,  Hiroyoshi Murata ,  Hiroyuki Hamagawa

IPC分类号： G09G3/20 ,  G09G3/36 ,  G09G3/28 ,  G09G3/30 ,  G09G5/10

CPC分类号： G09G3/3648 ,  G09G2310/027 ,  G09G3/2007 ,  G09G3/2018

摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

公开(公告)号：US06459416B1

公开(公告)日：2002-10-01

申请号：US09265795

申请日：1999-03-10

申请人： Itsuo Sasaki ,  Yasoji Suzuki ,  Hirofumi Kato ,  Isao Arita ,  Toshio Yanagisawa ,  Kazuyoshi Yamamoto ,  Hiroyoshi Murata ,  Hiroyuki Hamagawa

发明人： Itsuo Sasaki ,  Yasoji Suzuki ,  Hirofumi Kato ,  Isao Arita ,  Toshio Yanagisawa ,  Kazuyoshi Yamamoto ,  Hiroyoshi Murata ,  Hiroyuki Hamagawa

IPC分类号： G09G328

CPC分类号： G09G3/3648 ,  G09G3/2007 ,  G09G3/2018 ,  G09G2310/027

摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

摘要翻译： 通过使用少量电压，设计用于显示无闪烁等的多灰度级图像的多灰度级显示器。 显示器包括：第一灰度级图形生成电路311，用于产生在m个帧周期期间获取灰度级的第一灰度级图形;第二灰度级图形生成电路321，用于生成获取另一灰度级图案的第二灰度级图案 在n个帧周期（n是大于m的正整数）的灰度级，以及根据来自第一灰度级图形生成电路311或第二灰度级图形生成电路311的输出，选择并输出预设电压之一的选择电路341 当输入的多灰度级显示数据对应于第一灰度级图案或第二灰度级图案的灰度级时，灰度级图形产生电路321。

公开(公告)号：US4546327A

公开(公告)日：1985-10-08

申请号：US513308

申请日：1983-07-13

申请人： Yasoji Suzuki ,  Itsuo Sasaki ,  Shouji Abou

发明人： Yasoji Suzuki ,  Itsuo Sasaki ,  Shouji Abou

IPC分类号： H03F3/20 ,  H03F3/213 ,  H03F3/45 ,  H03F3/72

CPC分类号： H03F3/213 ,  H03F3/45183 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/507 ,  H03F2200/522 ,  H03F2203/45508 ,  H03F2203/45674

摘要： A signal corresponding to an analog input signal is supplied to one of two input terminals of a two-input, one-output MOS differential amplifier. A reference voltage signal is supplied to the other of the two input terminals of the MOS differential amplifier. A bipolar transistor having one end connected to an analog signal output terminal is driven by a signal from the output terminal of the MOS differential amplifier. A loudspeaker is driven by the bipolar transistor.

摘要翻译： 对应于模拟输入信号的信号被提供给双输入一输出MOS差分放大器的两个输入端中的一个。 将参考电压信号提供给MOS差分放大器的两个输入端子中的另一个。 具有连接到模拟信号输出端的一端的双极晶体管由来自MOS差分放大器的输出端的信号驱动。 扬声器由双极晶体管驱动。

公开(公告)号：US4988894A

公开(公告)日：1991-01-29

申请号：US365739

申请日：1989-06-14

申请人： Akira Takiba ,  Hiroyoshi Murata ,  Yasoji Suzuki ,  Isao Abe

发明人： Akira Takiba ,  Hiroyoshi Murata ,  Yasoji Suzuki ,  Isao Abe

IPC分类号： H03K17/10 ,  H03K17/693

CPC分类号： H03K17/102 ,  H03K17/693

摘要： A power supply switching circuit includes first to third MOS transistors (P1, P2 and P3) connected in series between a high-potential source and a standard-potential source. The circuit performs a switching operation using a standard-potential and at least one potential which is different from the standard-poential, and outputs plural power supply potentials. The third MOS transistor (P3) is inserted between the first and second MOS transistors (P1 and P2). The back gate of the third transistor (P3) is connected to an output terminal (OUT1) formed between the second transistor (P2) and the third transistor (P3) and prevents the formation of a current path via turned-off transistor (P1) due to the action of a parasitic diode in the first and second transistors caused by potential fluctuations.

公开(公告)号：US4930105A

公开(公告)日：1990-05-29

申请号：US178609

申请日：1988-04-07

申请人： Osamu Matsumoto ,  Tadashi Maruyama ,  Hiroyoshi Murata ,  Isao Abe ,  Tomohisa Shigematsu ,  Kazuyoshi Shinada ,  Yasoji Suzuki ,  Ichiro Kobayashi

发明人： Osamu Matsumoto ,  Tadashi Maruyama ,  Hiroyoshi Murata ,  Isao Abe ,  Tomohisa Shigematsu ,  Kazuyoshi Shinada ,  Yasoji Suzuki ,  Ichiro Kobayashi

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/0425

摘要： A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

公开(公告)号：US06046626A

公开(公告)日：2000-04-04

申请号：US3946

申请日：1998-01-08

申请人： Yukihiro Saeki ,  Yasoji Suzuki

发明人： Yukihiro Saeki ,  Yasoji Suzuki

IPC分类号： G11C11/413 ,  G06K19/07 ,  G11C11/407 ,  G11C16/06 ,  H02M3/07 ,  H03K19/0948 ,  G05F3/02

CPC分类号： H02M3/073

摘要： A voltage transfer circuit comprises a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal, a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a clock signal, as well as a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the clock signal.

摘要翻译： 电压传输电路包括第一通道类型的第一MOS晶体管，其具有连接到被提供有预定电压的第一节点的漏极端子，连接到第二节点的源极端子和栅极端子，第一MOS晶体管的第一 沟道型，具有连接到第二节点的源极端子，连接到第一MOS晶体管的栅极端子的漏极端子和提供有时钟信号的栅极端子，以及具有第二沟道类型的第三MOS晶体管，其具有 漏极端子连接到第二MOS晶体管的漏极端子，连接到提供有参考电压的第三节点的源极端子和被提供有时钟信号的栅极端子。

公开(公告)号：US4558234A

公开(公告)日：1985-12-10

申请号：US652429

申请日：1984-09-20

申请人： Yasoji Suzuki ,  Kenji Matsuo

发明人： Yasoji Suzuki ,  Kenji Matsuo

IPC分类号： H03K19/017 ,  H03K19/0175 ,  H03K19/0944 ,  H03K19/092 ,  H03K19/003 ,  H03K19/01 ,  H03K19/094

CPC分类号： H03K19/09448 ,  H03K19/01721 ,  H03K19/017518

摘要： Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter with a pregiven ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and pregiven threshold voltages of the FETs so as to have an input voltage characteristic adapted to an output voltage characteristic, and a buffer circuit which includes a bipolar transistor for receiving at the base thereof a signal from the output terminal of the complementary MOS inverter and an N channel MOSFET for receiving at the gate thereof an input signal applied to the complementary MOS inverter. The inverter and buffer are connected in series to one another between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof.

摘要翻译： 公开了具有互补MOS反相器的互补MOSFET逻辑电路，其具有P沟道MOSFET和N沟道MOSFET的沟道宽度的预制比和FET的预定阈值电压，以便具有适于输出电压的输入电压特性 特性和缓冲电路，其包括用于在其基极处接收来自互补MOS反相器的输出端的信号的双极晶体管和用于在其栅极处接收施加到互补MOS反相器的输入信号的N沟道MOSFET。 反相器和缓冲器在高电位施加点和低电位施加点之间彼此串联连接，并且在其输出端产生与互补MOS反相器的逻辑输出信号相对应的信号。

公开(公告)号：US4280272A

公开(公告)日：1981-07-28

申请号：US85595

申请日：1979-10-17

申请人： Hideharu Egawa ,  Koji Matsuki ,  Yasoji Suzuki

发明人： Hideharu Egawa ,  Koji Matsuki ,  Yasoji Suzuki

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L21/823807 ,  H01L27/0928

摘要： A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

摘要翻译： 互补半导体器件包括分别形成在半导体衬底中并具有基本相同的杂质浓度的P型和N型半导体区域。 N沟道型和P沟道型硅栅极场效应晶体管分别形成在P沟道型和N沟道型区域中。 P型和N沟道型硅栅场效应晶体管的栅电极由相同导电类型的多晶硅形成。 相同导电类型的杂质被掺杂到两个半导体区域中以提供沟道掺杂区域。

公开(公告)号：US4264968A

公开(公告)日：1981-04-28

申请号：US864714

申请日：1977-12-27

申请人： Yasoji Suzuki ,  Fuminari Tanaka ,  Yasushi Sato

发明人： Yasoji Suzuki ,  Fuminari Tanaka ,  Yasushi Sato

IPC分类号： G01R19/00 ,  G04G3/02 ,  G04G9/00 ,  G04G99/00 ,  G04C3/00

CPC分类号： G04G99/00 ,  G04G3/022

摘要： There is provided an electronic timepiece basic circuit comprising a pulse generating circuit for generating 1 Hz pulses, a first terminal group having a plurality of terminals including a terminal connected to the output terminal of the pulse generating circuit, a second terminal group having terminals to be connected to the terminals of the first terminal group, respectively, 10 scale counters coupled with the second terminal group, 6 scale counters connected to the 10 scale counters, a display unit, and a decoder which is coupled with the 10 scale counters and the 6 scale counters and decodes the contents of the 10 and 6 scale counters and delivers the decoded contents to the display unit. The first and second terminal groups are properly coupled to each other. The combination of the 10 scale counters and the 6 scale counters is properly modified so as to form a 12, 24, or 60 scale counter, as necessary.

摘要翻译： 提供了一种电子钟表基本电路，包括用于产生1Hz脉冲的脉冲发生电路，具有包括连接到脉冲发生电路的输出端的端子的多个端子的第一端子组，具有端子的第二端子组 分别连接到第一终端组的终端，与第二终端组耦合的10个比例计数器，连接到10个比例计数器的6个比例计数器，显示单元和与10个比例计数器耦合的解码器，6 缩放计数器并解码10和6比例计数器的内容，并将解码的内容传送到显示单元。 第一和第二端子组彼此适当地联接。 10个刻度计数器和6个刻度计数器的组合被适当修改，以便根据需要形成12个，24个或60个刻度计数器。

公开(公告)号：US4255678A

公开(公告)日：1981-03-10

申请号：US962221

申请日：1978-11-20

申请人： Yasoji Suzuki ,  Kiyofumi Ochii ,  Hirozi Asahi

发明人： Yasoji Suzuki ,  Kiyofumi Ochii ,  Hirozi Asahi

IPC分类号： G11C11/41 ,  G11C11/409 ,  G11C11/419 ,  H03K5/24 ,  G11C7/00

CPC分类号： G11C11/419

摘要： A voltage sense circuit in which first and second parallel connections of complementary MOS transistors are connected between a pair of signal lines connected to memory cells and outputs of a flip-flop circuit for detecting a potential change of the signal line caused by data readout from an accessed memory cell. MOS transistors of one channel type in the parallel connections are adapted to precharge output node capacitors of the flip-flop circuit to a supply voltage level, while MOS transistors of the other channel type are adapted to couple complementary output voltage levels of the flip-flop circuit produced after the data readout and operation of the flip-flop circuit to the signal lines. Use of the parallel connections of complementary MOS transistors enables the application of a single power source for producing gate signals of these MOS transistors.

摘要翻译： 一种电压检测电路，其中互补MOS晶体管的第一和第二并联连接在连接到存储单元的一对信号线之间，并且用于检测由数据读出引起的信号线的电位变化的触发器电路的输出 存取存储单元 并联连接中的一个通道类型的MOS晶体管适于将触发器电路的输出节点电容器预充电到电源电压电平，而另一个通道类型的MOS晶体管适于耦合触发器的互补输出电压电平 在触发电路的数据读出和操作到信号线之后产生的电路。 使用互补MOS晶体管的并联连接使得能够应用单个电源来产生这些MOS晶体管的栅极信号。