公开(公告)号：US11736104B2

公开(公告)日：2023-08-22

申请号：US17633160

申请日：2020-10-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke Kinoshita ,  Hidetoshi Ishida ,  Hiroyuki Handa ,  Yuji Kudoh ,  Satoshi Nakazawa

IPC: H03K3/00 ,  H03K17/687 ,  G01R31/26

CPC classification number: H03K17/687 ,  G01R31/2621

Abstract: A switch system includes a bidirectional switch, a first gate driver circuit, a second gate driver circuit, a control unit, a first decision unit, and a second decision unit. The bidirectional switch includes a first source, a second source, a first gate, and a second gate. The first decision unit determines, based on a voltage at the first gate and a first threshold voltage, a state of the first gate in a first period in which a signal to turn OFF the first gate is output from the control unit to the first gate driver circuit. The second decision unit determines, based on a voltage at the second gate and a second threshold voltage, a state of the second gate in a second period in which a signal to turn OFF the second gate is output from the control unit to the second gate driver circuit.

公开(公告)号：US10128363B2

公开(公告)日：2018-11-13

申请号：US14736665

申请日：2015-06-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Satoshi Nakazawa ,  Tetsuzo Ueda

IPC: H01L29/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/51 ,  H01L29/10

Abstract: Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InxAlyGa1-(x+y)N layer on the InAlN layer, where 0

公开(公告)号：US12143098B2

公开(公告)日：2024-11-12

申请号：US17998658

申请日：2021-04-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke Kinoshita ,  Yuta Nagatomi ,  Ryosuke Maeda ,  Satoshi Nakazawa

IPC: H03K17/082

Abstract: A power loss of a switching device is suppressed. Circuit for a switching device is used in switching device. Switching device includes first path and second path. First path includes first field effect transistor and first inductor. Second path includes second field effect transistor and second inductor. First path and second path are connected in parallel to power supply. A first maximum current that is a maximum current during conduction of first field effect transistor is smaller than a second maximum current that is a maximum current during conduction of second field effect transistor. Circuit for a switching device includes processing part. Processing part executes a specific operation according to a voltage difference between voltage across first inductor and voltage across second inductor.

公开(公告)号：US09666664B2

公开(公告)日：2017-05-30

申请号：US14663140

申请日：2015-03-19

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ryo Kajitani ,  Tetsuzo Ueda ,  Yoshiharu Anda ,  Naohiro Tsurumi ,  Satoshi Nakazawa

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/0611 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78

Abstract: An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.