公开(公告)号：US11356663B2

公开(公告)日：2022-06-07

申请号：US17018320

申请日：2020-09-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Toshihiko Kusakabe ,  Shinji Kitamura ,  Takashi Hashimoto ,  Kiyofumi Abe ,  Hideyuki Ohgose

IPC: H04N19/117 ,  H04N19/119 ,  H04N19/174 ,  H04N19/176 ,  H04N19/82

Abstract: An encoder which encodes a picture includes processing circuitry and memory. Using the memory, the processing circuitry: splits the picture into a plurality of slice segments; encodes a plurality of blocks included in each of the plurality of slice segments; reconstructs the plurality of blocks encoded; adds, for each of the plurality of slice segments, control information to a header area of the slice segment, the control information being for controlling application of a filter to the slice segment; and applies, for each of the plurality of slice segments, the filter to a block which has been reconstructed in the slice segment, according to the control information of the slice segment.

公开(公告)号：US11297329B2

公开(公告)日：2022-04-05

申请号：US16382919

申请日：2019-04-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Toshihiko Kusakabe ,  Shinji Kitamura ,  Kiyofumi Abe ,  Hideyuki Ohgose ,  Takashi Hashimoto

IPC: H04N19/146 ,  H04N19/176 ,  H04N19/174 ,  H04N19/119 ,  H04N19/15 ,  H04N19/169

Abstract: Provided is an image encoding method which inhibits deterioration in processing performance for encoding while improving transmission efficiency. The image encoding method is for generating a bitstream by encoding a picture, and includes: sequentially encoding blocks included in the picture; deriving an encoding amount of a slice segment each time one of the blocks is encoded as a current block, the slice segment including the current block; determining whether the encoding amount derived is at least a threshold; and setting end information indicating an end of the slice segment in a position in the bitstream when the encoding amount is determined to be at least the threshold, the position corresponding to the current block encoded.

公开(公告)号：US10212442B2

公开(公告)日：2019-02-19

申请号：US15293759

申请日：2016-10-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Toshihiko Kusakabe ,  Kiyofumi Abe ,  Hideyuki Ohgose ,  Shinji Kitamura ,  Takashi Hashimoto ,  Yuki Maruyama ,  Tatsuro Juri

IPC: H04B1/66 ,  H04N19/436 ,  H04N19/70

Abstract: The image encoding apparatus which encodes, on a per block basis, a current picture included in a moving picture includes: an encoder which outputs a first encoded stream including, in the following arrangement order, (i) slice data obtained by encoding a slice included in the current picture and including a plurality of block lines and (ii) a slice header including information indicating a code amount of each of the plurality of block lines; and an exchanger which exchanges arrangement positions of the slice data and the slice header in the first encoded stream.

公开(公告)号：US10116945B2

公开(公告)日：2018-10-30

申请号：US15298603

申请日：2016-10-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kiyofumi Abe ,  Hideyuki Ohgose ,  Shinji Kitamura ,  Takashi Hashimoto ,  Toshihiko Kusakabe ,  Yuki Maruyama ,  Tatsuro Juri

IPC: H04N19/174 ,  H04N19/196 ,  H04N19/159 ,  H04N19/115

Abstract: A moving picture encoding apparatus encodes a moving picture having an interlaced structure, and includes: a storage which stores fields as reference pictures; and an encoder which encodes a current field as a B-picture, using a first reference picture list which includes only one field in a same parity as the current field, and a second reference picture list which includes only one field in an opposite parity to the current field.

公开(公告)号：US09641868B2

公开(公告)日：2017-05-02

申请号：US14629747

申请日：2015-02-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Amano ,  Takeshi Tanaka ,  Takashi Hashimoto ,  Yoshiteru Hayashi

IPC: H04N19/82 ,  H04N19/51 ,  H04N19/61 ,  H04N19/117 ,  H04N19/44 ,  H04N19/43 ,  H04N19/513

CPC classification number: H04N19/82 ,  H04N19/117 ,  H04N19/43 ,  H04N19/44 ,  H04N19/513 ,  H04N19/61

Abstract: A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit (101) which decodes, from a coded stream, a plurality of motion compensation filter coefficients; a memory (109) for holding the motion compensation filter coefficients included in the coded stream; a filter coefficient storage unit (103) for holding at least one of the motion compensation filter coefficients which is required for the motion compensation; a motion compensation unit (107) which performs motion compensation using the required motion compensation filter coefficient held in the filter coefficient storage unit; and a filter coefficient transfer control unit (102) which writes, in the memory, the motion compensation filter coefficients decoded by the decoding unit, and transfers the required motion compensation filter coefficient from the memory to the filter coefficient storage unit, only when the required coefficient is not yet stored therein.

公开(公告)号：US09267986B2

公开(公告)日：2016-02-23

申请号：US14806059

申请日：2015-07-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takashi Hashimoto ,  Takashi Morimoto

IPC: H01L21/66 ,  G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2887 ,  G01R31/2801 ,  G01R31/2853 ,  G01R31/2889 ,  G01R31/318513 ,  H01L22/10 ,  H01L22/14 ,  H01L25/0657 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested.