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12 条记录 (耗时 0.02 秒)

    Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system
    2.
    发明授权
    Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system 失效
    在总线上交织读写操作，并最大限度地减少计算机系统内存模块的缓冲

    公开(公告)号：US06807609B1

    公开(公告)日：2004-10-19

    申请号：US08067262

    申请日：1993-05-25

    申请人： Paul J. Lemmon ,  Raj Ramanujan

    发明人： Paul J. Lemmon ,  Raj Ramanujan

    IPC分类号： G06F1328

    CPC分类号： G06F13/161

    摘要： A computer system is adapted to transfer write data from a central processing unit to one of a plurality of memory modules in a memory array by transferring a block of write data to a memory control logic device. The memory control logic device transfers the block of data in a plurality of data bursts interspaced by a preselected number of bus cycles. During the interspaced preselected number of bus cycles, the memory control logic device sends pending read commands to an available memory module thereby overlapping read and write operations on the memory bus, thus, lowering memory read latency.

    摘要翻译： 计算机系统适于通过将写入数据块传送到存储器控制逻辑器件将写入数据从中央处理单元传送到存储器阵列中的多个存储器模块之一。 存储器控制逻辑器件以预先选择的总线周期数间隔的多个数据突发传送数据块。 在间隔预选数量的总线周期期间，存储器控制逻辑器件将待处理的读取命令发送到可用的存储器模块，从而在存储器总线上重叠读取和写入操作，从而降低存储器读取等待时间。

    High speed bus system that incorporates uni-directional point-to-point buses
    4.
    发明授权
    High speed bus system that incorporates uni-directional point-to-point buses 失效
    采用单向点对点总线的高速总线系统

    公开(公告)号：US06928500B1

    公开(公告)日：2005-08-09

    申请号：US08883118

    申请日：1997-06-26

    申请人： Raj Ramanujan ,  James B. Keller ,  William A. Samaras ,  John Derosa ,  Robert E. Stewart

    发明人： Raj Ramanujan ,  James B. Keller ,  William A. Samaras ,  John Derosa ,  Robert E. Stewart

    IPC分类号： G06F15/167 ,  G06F15/173 ,  H04L12/28 ,  H04L12/403 ,  G06F13/14 ,  G06F13/36

    CPC分类号： H04L12/403 ,  G06F15/167 ,  G06F15/173 ,  H04L12/4625

    摘要： A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

    摘要翻译： 一种用于共享存储器系统的高速总线系统，其允许多个处理器与多处理器共享存储器系统的存储器阵列之间的命令和数据的高速传输，其中高速总线系统包括 中央单元和连接在多个处理器和共享存储器之间的一系列单向总线，中央单元包括仲裁逻辑和一系列多路复用器，以确定哪些CPU被授权访问共享总线，调度逻辑与 仲裁逻辑和多路复用器，以确定哪些CPU被授权访问共享总线，以及端口逻辑，用于组合CPU传输并确定这些传输是否有效。

    Method and apparatus for sharing data between processors in a computer system
    7.
    发明授权
    Method and apparatus for sharing data between processors in a computer system 失效
    用于在计算机系统中的处理器之间共享数据的方法和装置

    公开(公告)号：US5263144A

    公开(公告)日：1993-11-16

    申请号：US546508

    申请日：1990-06-29

    申请人： John H. Zurawski ,  Raj Ramanujan ,  John De Rosa

    发明人： John H. Zurawski ,  Raj Ramanujan ,  John De Rosa

    IPC分类号： G06F12/08 ,  G06F13/14

    CPC分类号： G06F12/0831

    摘要： A cache coherency scheme in a multiprocessor computer system allows data sharing between caches at a fast rate. A new cache coherency state is introduced which allows a processor pair to more effectively share data and eliminate bus transfers thereby improving system throughput. The transfer of data is accomplished by the returning a portion of a preselected data block pursuant to either a read or a read for ownership request by a first one of the processors of the processor pair by the second processor of the processor pair. The ownership of the portion of the preselected data block is shared by the processor pair. Both processors set an indicator to denote that the preselected data block is an incomplete data block.

    摘要翻译： 多处理器计算机系统中的高速缓存一致性方案允许以高速率在高速缓存之间进行数据共享。 引入了新的高速缓存一致性状态，允许处理器对更有效地共享数据并消除总线传输，从而提高系统吞吐量。 通过处理器对的第二处理器由处理器对的第一处理器的所有权请求的读取或读取来返回预选数据块的一部分来实现数据的传送。 预选数据块的部分的所有权由处理器对共享。 两个处理器设置一个指示符，表示预先选择的数据块是不完整的数据块。

    Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
    8.
    发明授权
    Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus 失效
    在多处理器系统中控制共享存储器总线以防止总线冲突并确保完整总线的方法

    公开(公告)号：US5202973A

    公开(公告)日：1993-04-13

    申请号：US546548

    申请日：1990-06-29

    申请人： Raj Ramanujan ,  James B. Keller ,  Jay Stickney ,  Steven Ho ,  Paul Lemmon

    发明人： Raj Ramanujan ,  James B. Keller ,  Jay Stickney ,  Steven Ho ,  Paul Lemmon

    IPC分类号： G06F13/16 ,  G06F13/376

    CPC分类号： G06F13/161 ,  G06F13/376

    摘要： A system and method for controlling a shared memory bus in a computer of a multi-processor system prevents collisions on the shared bus and ensures that the bus is full at system start-up. Steady state operations are maintained without the need for a queuing mechanism in the system's memory controller and in view of the memory modules of the shared memory having different read access times, with the system and method being implemented in a system that includes a central unit and multiple uni-directional buses that are disposed between a shared memory and a plurality of processors, with the central unit controlling access to, and use of, the shared buses of the system.

    摘要翻译： 用于控制多处理器系统的计算机中的共享存储器总线的系统和方法防止共享总线上的冲突，并确保总线在系统启动时已满。 维持稳定状态操作，而不需要系统存储器控制器中的排队机制，并且考虑到具有不同读取访问时间的共享存储器的存储器模块，系统和方法在包括中央单元和 多个单向总线设置在共享存储器和多个处理器之间，中央单元控制对系统的共享总线的访问和使用。