Embedded barrier for dielectric encapsulation
    1.
    发明申请
    Embedded barrier for dielectric encapsulation 有权
    介质封装的嵌入式屏障

    公开(公告)号:US20070057374A1

    公开(公告)日:2007-03-15

    申请号:US11162513

    申请日:2005-09-13

    IPC分类号: H01L23/52 H01L21/4763

    摘要: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.

    摘要翻译: 一种半导体互连结构和方法,提供嵌入的阻挡层,以防止在化学机械抛光期间或之后损坏电介质材料。 该方法采用嵌入膜,回蚀,使用选择性CoWP或诸如SiCNH膜的共形盖的组合来保护介电材料免受CMP工艺以及随后的下一个互连级别的蚀刻,清洁和沉积步骤 。