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1.发明授权Implanted barrier layer to improve line reliability and method of forming same 有权植入障碍层提高线路可靠性及其形成方法公开(公告)号：US06992004B1
公开(公告)日：2006-01-31
申请号：US10209060
申请日：2002-07-31
申请人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
发明人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76859 , H01L21/76867
摘要： A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.
摘要翻译： 用于制造具有改善的电迁移特性的集成电路的方法包括在层间电介质层中形成孔，并在孔中提供阻挡层。 孔被金属材料填充，并且在金属材料上方设有阻挡层。 可以在金属材料和阻挡层的界面处形成金属间化合物区域。 金属间化合物可以通过种植物形成。
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2.发明授权Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效使用化学气相沉积（CVD）铜沉积的粘附前体层的方法公开(公告)号：US07169706B2
公开(公告)日：2007-01-30
申请号：US10687186
申请日：2003-10-16
申请人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译： 示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。 该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。 粘附前体层由气体形成，电介质材料包括孔。
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3.发明授权Method of forming a metal or metal nitride interface layer between silicon nitride and copper 有权在氮化硅和铜之间形成金属或金属氮化物界面层的方法公开(公告)号：US06518167B1
公开(公告)日：2003-02-11
申请号：US10123588
申请日：2002-04-16
申请人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
发明人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/28562 , H01L21/76834
摘要： A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.
摘要翻译： 在铜层和氮化硅层之间形成金属或金属氮化物层界面的方法可以包括在铜层上提供金属有机气体或金属/金属氮化物前体，从金属或金属氮化物层之间的反应形成金属或金属氮化物层 有机气体或金属/金属氮化物前体和铜层，以及在金属或金属氮化物层和铜层上沉积氮化硅层。 金属或金属氮化物层可以在氮化硅层和铜层之间提供更好的界面粘合性。 金属层可以改善铜层和氮化硅层之间的界面，提高电迁移可靠性，从而提高集成电路器件的性能。
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公开(公告)号：US06589408B1
公开(公告)日：2003-07-08
申请号：US10107778
申请日：2002-03-27
IPC分类号： C23C1435
CPC分类号： C23C14/3414 , C23C14/3407
摘要： A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a first alloy concentration and a side annular section having a second alloy concentration. The side annular section has ends coupled to ends of the top planar section. The first alloy concentration and the second alloy concentration are different.
摘要翻译： 非平面靶可以被配置用于等离子体气相沉积（PVD）工艺，其中离子轰击非平面靶，并使存在于非平面靶中的合金原子被敲击松动并形成合金膜层。 目标包括具有第一合金浓度的顶部平面部分和具有第二合金浓度的侧部环形部分。 侧面环形部分具有端部连接到顶部平面部分的端部。 第一合金浓度和第二合金浓度不同。
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5.发明授权Method of forming an adhesion layer with an element reactive with a barrier layer 失效用与阻挡层反应的元件形成粘合层的方法公开(公告)号：US06861349B1
公开(公告)日：2005-03-01
申请号：US10145944
申请日：2002-05-15
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76859 , H01L21/76873 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.
摘要翻译： 一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金 元素进入阻挡材料层上的界面层，在界面层上沉积合金层。 植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。
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公开(公告)号：US06815340B1
公开(公告)日：2004-11-09
申请号：US10145928
申请日：2002-05-15
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76846 , H01L21/76849 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.
摘要翻译： 制造集成电路的方法可以包括执行反应离子蚀刻（RIE）以在电介质层中形成通孔，其中通孔孔暴露位于电介质层下面的导电层的一部分，从RIE除去聚合物残余物， 以及使用合金在导电层的暴露部分上形成成核层。 成核层可以在无电解过程中形成，并且可以提高电迁移可靠性，降低通孔电阻，消除通孔腐蚀，并消除电介质侧壁上的铜再溅射。
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公开(公告)号：US06724087B1
公开(公告)日：2004-04-20
申请号：US10331682
申请日：2002-12-30
申请人： Matthew S. Buynoski , Paul R. Besser , Sergey D. Lopatin , Lu You
发明人： Matthew S. Buynoski , Paul R. Besser , Sergey D. Lopatin , Lu You
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/76847 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at least one interconnect layer, the interconnect layer including a number of conductive lines. Each of the conductive lines includes a first thin barrier layer, a first thin copper layer, a second thin barrier layer and a second thin copper layer. The layered or laminated structure can reduce unconstrained void formation.
摘要翻译： 集成电路的制造方法可以包括形成叠层导电线。 层叠导电线可以形成在电介质沟槽中。 层叠导电线可以包括交替的阻挡层和铜层。 集成电路包括至少一个互连层，所述互连层包括多个导电线。 每个导线包括第一薄势垒层，第一薄铜层，第二薄阻挡层和第二薄铜层。 分层或层压结构可以减少无约束的空隙形成。
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8.发明授权Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect 有权使用三元铜合金获得低电阻和大晶粒尺寸互连的方法公开(公告)号：US07696092B2
公开(公告)日：2010-04-13
申请号：US09994395
申请日：2001-11-26
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/2885 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.
摘要翻译： 一种制造集成电路的方法包括沿着横向侧壁和通孔孔的底部形成阻挡层，并且在通孔中通过材料提供三元铜合金以形成通孔。 通孔被配置成通过材料接收三元铜合金并电连接第一导电层和第二导电层。 三元铜合金通孔材料有助于通孔具有较低的电阻和增加的晶粒尺寸与人工晶界。
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9.发明授权Method of self-annealing conductive lines that separates grain size effects from alloy mobility 有权将晶粒尺寸效应与合金迁移率分离的导电线自退火方法公开(公告)号：US06979642B1
公开(公告)日：2005-12-27
申请号：US10628733
申请日：2003-07-28
IPC分类号： H01L21/283 , H01L21/288 , H01L21/321 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/321 , H01L21/76877
摘要： A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.
摘要翻译： 形成诸如铜导电结构，管线或通孔的导电结构的方法被优化用于合金元件的大晶粒生长和分布。 合金元素可以减少与导电结构相关的电迁移问题。 导电结构在较长时间内在低温过程中自退火或首先退火。 利用另一退火来分配合金元素。
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10.发明授权公开(公告)号：US06835655B1
公开(公告)日：2004-12-28
申请号：US09994397
申请日：2001-11-26
IPC分类号： H01L2144
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76859 , H01L2924/0002 , H01L2924/00
摘要： A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper layer to form a barrier material layer separating the via from the copper layer, implanting a metal species into the barrier material layer, and providing a conductive layer over the via such that the via electrically connects the conductive layer to the copper layer. The implanted metal species can make the barrier material layer more resistant to copper diffusion from the copper layer.
摘要翻译： 在集成电路制造工艺中注入铜阻挡材料以提高电性能的方法可以包括在集成电路基板上提供铜层，在位于铜层上方的通孔的底部和侧面提供阻挡材料以形成屏障 将所述通孔与所述铜层分离的材料层，将金属物质注入到所述阻挡材料层中，以及在所述通孔上方提供导电层，使得所述通孔将所述导电层电连接到所述铜层。 注入的金属物质可以使阻挡材料层更能抵抗铜层从铜层扩散。
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