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1.发明授权Method of self-annealing conductive lines that separates grain size effects from alloy mobility 有权将晶粒尺寸效应与合金迁移率分离的导电线自退火方法公开(公告)号：US06979642B1
公开(公告)日：2005-12-27
申请号：US10628733
申请日：2003-07-28
IPC分类号： H01L21/283 , H01L21/288 , H01L21/321 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/321 , H01L21/76877
摘要： A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.
摘要翻译： 形成诸如铜导电结构，管线或通孔的导电结构的方法被优化用于合金元件的大晶粒生长和分布。 合金元素可以减少与导电结构相关的电迁移问题。 导电结构在较长时间内在低温过程中自退火或首先退火。 利用另一退火来分配合金元素。
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2.发明授权Method of forming a metal or metal nitride interface layer between silicon nitride and copper 有权在氮化硅和铜之间形成金属或金属氮化物界面层的方法公开(公告)号：US06518167B1
公开(公告)日：2003-02-11
申请号：US10123588
申请日：2002-04-16
申请人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
发明人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/28562 , H01L21/76834
摘要： A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.
摘要翻译： 在铜层和氮化硅层之间形成金属或金属氮化物层界面的方法可以包括在铜层上提供金属有机气体或金属/金属氮化物前体，从金属或金属氮化物层之间的反应形成金属或金属氮化物层 有机气体或金属/金属氮化物前体和铜层，以及在金属或金属氮化物层和铜层上沉积氮化硅层。 金属或金属氮化物层可以在氮化硅层和铜层之间提供更好的界面粘合性。 金属层可以改善铜层和氮化硅层之间的界面，提高电迁移可靠性，从而提高集成电路器件的性能。
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3.发明授权Implanted barrier layer to improve line reliability and method of forming same 有权植入障碍层提高线路可靠性及其形成方法公开(公告)号：US06992004B1
公开(公告)日：2006-01-31
申请号：US10209060
申请日：2002-07-31
申请人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
发明人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76859 , H01L21/76867
摘要： A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.
摘要翻译： 用于制造具有改善的电迁移特性的集成电路的方法包括在层间电介质层中形成孔，并在孔中提供阻挡层。 孔被金属材料填充，并且在金属材料上方设有阻挡层。 可以在金属材料和阻挡层的界面处形成金属间化合物区域。 金属间化合物可以通过种植物形成。
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公开(公告)号：US20080150011A1
公开(公告)日：2008-06-26
申请号：US11958646
申请日：2007-12-18
申请人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
发明人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.
摘要翻译： 提供一种用于形成集成电路系统的方法，包括形成具有芯区域和周边区域的衬底，在芯区域中的衬底上形成电荷存储堆叠，形成具有堆叠集管的栅极堆叠，堆叠集束具有金属部分 衬底，并且在电荷存储堆叠上形成具有堆叠头的存储器系统。
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5.发明授权公开(公告)号：US07217660B1
公开(公告)日：2007-05-15
申请号：US11109964
申请日：2005-04-19
IPC分类号： H01L21/22
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76843 , H01L21/76846 , H01L29/6659
摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.
摘要翻译： 一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。 在设置在半导体衬底上的电介质层中形成接触开口。 接触开口露出半导体衬底的一部分。 在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。 硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。 氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。 在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。
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公开(公告)号：US20080149990A1
公开(公告)日：2008-06-26
申请号：US11735241
申请日：2007-04-13
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114
摘要： A memory system includes a substrate, forming an insulator over the substrate, forming a gate layer over the insulator, forming a stability layer over the gate layer, and forming a conductive layer over the stability layer.
摘要翻译： 存储器系统包括：衬底，在衬底上形成绝缘体，在绝缘体上形成栅极层，在栅极层上形成稳定层，并在稳定层上形成导电层。
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7.发明授权公开(公告)号：US07407882B1
公开(公告)日：2008-08-05
申请号：US10928665
申请日：2004-08-27
申请人： Connie Pin-Chin Wang , Paul R. Besser , Wen Yu , Jinsong Yin , Keizaburo Yoshie
发明人： Connie Pin-Chin Wang , Paul R. Besser , Wen Yu , Jinsong Yin , Keizaburo Yoshie
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76856
摘要： A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer and exposes a portion of the semiconductor substrate. Titanium silicide is disposed on the dielectric layer, sidewalls, and the exposed portion of the semiconductor substrate. The titanium silicide may be formed by disposing titanium on the dielectric layer, sidewalls, and exposed portion of the semiconductor substrate and reacting the titanium with silane. Alternatively, the titanium silicide may be sputter deposited. A layer of titanium nitride is formed on the titanium silicide. A layer of tungsten is formed on the titanium nitride. The tungsten, titanium nitride, and titanium silicide are polished to form the contact structures.
摘要翻译： 具有硅化钛接触结构的半导体部件和半导体部件的制造方法。 在半导体衬底上形成介电材料层。 在电介质层中形成具有侧壁的开口，并露出半导体衬底的一部分。 钛硅化物设置在电介质层，侧壁和半导体衬底的暴露部分上。 钛硅化物可以通过在电介质层，侧壁和半导体衬底的暴露部分上设置钛并使钛与硅烷反应而形成。 或者，可以溅射沉积钛硅化物。 在硅化钛上形成氮化钛层。 在氮化钛上形成钨层。 将钨，氮化钛和硅化钛抛光以形成接触结构。
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8.发明授权公开(公告)号：US09202758B1
公开(公告)日：2015-12-01
申请号：US11109965
申请日：2005-04-19
IPC分类号： H01L21/8234 , H01L29/49
CPC分类号： H01L21/823418 , H01L21/02129 , H01L21/02271 , H01L21/28556 , H01L21/28562 , H01L21/76801 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/485 , H01L23/53266 , H01L23/53295 , H01L29/4975 , H01L29/665 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and a method for manufacturing the semiconductor component that are suitable for use with low temperature processing. A semiconductor substrate is provided and an optional layer of silicon nitride is formed on the semiconductor substrate using Atomic Layer Deposition (ALD). A layer of dielectric material is formed on the silicon nitride layer using Sub-Atmospheric Chemical Vapor Deposition (SACVD) at a temperature below about 450° C. When the optional layer of silicon nitride is not present, the SACVD dielectric material is formed on the semiconductor substrate. A contact hole having sidewalls is formed through the SACVD dielectric layer, through the silicon nitride layer, and exposes a portion of the semiconductor substrate. A layer of tungsten nitride is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact hole. Tungsten is formed on the layer of tungsten nitride.
摘要翻译： 适用于低温处理的半导体元件和半导体元件的制造方法。 提供半导体衬底，并且使用原子层沉积（ALD）在半导体衬底上形成任选的氮化硅层。 使用亚大气化学气相沉积（SACVD）在低于约450℃的温度下在氮化硅层上形成介电材料层。当不存在任选的氮化硅层时，SACVD介电材料形成在 半导体衬底。 通过SACVD介电层，通过氮化硅层形成具有侧壁的接触孔，并露出半导体衬底的一部分。 在半导体衬底的暴露部分和接触孔的侧壁上形成氮化钨层。 在氮化钨层上形成钨。
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公开(公告)号：US20080153224A1
公开(公告)日：2008-06-26
申请号：US11735229
申请日：2007-04-13
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： An integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a contact on the outer doped region, thinning the contact for forming a thinned contact, and forming a metal plug on the thinned contact.
摘要翻译： 提供了一种集成电路系统，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在外部掺杂区域上形成接触，减少接触以形成变薄的接触，以及 在变薄的触点上形成金属插头。
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公开(公告)号：US06589408B1
公开(公告)日：2003-07-08
申请号：US10107778
申请日：2002-03-27
IPC分类号： C23C1435
CPC分类号： C23C14/3414 , C23C14/3407
摘要： A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a first alloy concentration and a side annular section having a second alloy concentration. The side annular section has ends coupled to ends of the top planar section. The first alloy concentration and the second alloy concentration are different.
摘要翻译： 非平面靶可以被配置用于等离子体气相沉积（PVD）工艺，其中离子轰击非平面靶，并使存在于非平面靶中的合金原子被敲击松动并形成合金膜层。 目标包括具有第一合金浓度的顶部平面部分和具有第二合金浓度的侧部环形部分。 侧面环形部分具有端部连接到顶部平面部分的端部。 第一合金浓度和第二合金浓度不同。
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