METHOD AND APPARATUS FOR DIAGNOSING BROKEN SCAN CHAIN BASED ON LEAKAGE LIGHT EMISSION
    1.
    发明申请
    METHOD AND APPARATUS FOR DIAGNOSING BROKEN SCAN CHAIN BASED ON LEAKAGE LIGHT EMISSION 失效
    用于诊断基于泄漏光发射的断路扫描链的方法和装置

    公开(公告)号:US20080208507A1

    公开(公告)日:2008-08-28

    申请号:US12115768

    申请日:2008-05-06

    IPC分类号: G01R31/02

    CPC分类号: G01R31/318538 G01R31/311

    摘要: A mechanism for diagnosing broken scan chains based on leakage light emission is provided. An image capture mechanism detects light emission from leakage current in complementary metal oxide semiconductor (CMOS) devices. The diagnosis mechanism identifies devices with unexpected light emission. An unexpected amount of light emission may indicate that a transistor is turned off when it should be turned on or vice versa. All possible inputs may be tested to determine whether a problem exists with transistors in latches or with transistors in clock buffers. Broken points in the scan chain may then be determined based on the locations of unexpected light emission.

    摘要翻译: 提供了一种基于泄漏光发射来诊断断层扫描链的机构。 图像捕获机构检测互补金属氧化物半导体(CMOS)器件中的泄漏电流的发光。 诊断机制识别具有意外发光的设备。 意外的发光量可能表明当它应该被打开时晶体管被关闭,反之亦然。 可以测试所有可能的输入以确定锁存器中的晶体管或时钟缓冲器中的晶体管是否存在问题。 然后可以基于意外光发射的位置来确定扫描链中的断点。

    Method and apparatus for diagnosing broken scan chain based on leakage light emission
    2.
    发明授权
    Method and apparatus for diagnosing broken scan chain based on leakage light emission 失效
    基于泄漏光发射诊断断层扫描链的方法和装置

    公开(公告)号:US07788058B2

    公开(公告)日:2010-08-31

    申请号:US12115768

    申请日:2008-05-06

    IPC分类号: G06F19/00

    CPC分类号: G01R31/318538 G01R31/311

    摘要: A mechanism for diagnosing broken scan chains based on leakage light emission is provided. An image capture mechanism detects light emission from leakage current in complementary metal oxide semiconductor (CMOS) devices. The diagnosis mechanism identifies devices with unexpected light emission. An unexpected amount of light emission may indicate that a transistor is turned off when it should be turned on or vice versa. All possible inputs may be tested to determine whether a problem exists with transistors in latches or with transistors in clock buffers. Broken points in the scan chain may then be determined based on the locations of unexpected light emission.

    摘要翻译: 提供了一种基于泄漏光发射来诊断断层扫描链的机构。 图像捕获机构检测互补金属氧化物半导体(CMOS)器件中的泄漏电流的发光。 诊断机制识别具有意外发光的设备。 意外的发光量可能表明当它应该被打开时晶体管被关闭,反之亦然。 可以测试所有可能的输入以确定锁存器中的晶体管或时钟缓冲器中的晶体管是否存在问题。 然后可以基于意外光发射的位置来确定扫描链中的断点。

    Method and apparatus for diagnosing broken scan chain based on leakage light emission
    3.
    发明授权
    Method and apparatus for diagnosing broken scan chain based on leakage light emission 失效
    基于泄漏光发射诊断断层扫描链的方法和装置

    公开(公告)号:US07426448B2

    公开(公告)日:2008-09-16

    申请号:US10771218

    申请日:2004-02-03

    IPC分类号: G06F19/00

    CPC分类号: G01R31/318538 G01R31/311

    摘要: A mechanism for diagnosing broken scan chains based on leakage light emission is provided. An image capture mechanism detects light emission from leakage current in complementary metal oxide semiconductor (CMOS) devices. The diagnosis mechanism identifies devices with unexpected light emission. An unexpected amount of light emission may indicate that a transistor is turned off when it should be turned on or vice versa. All possible inputs may be tested to determine whether a problem exists with transistors in latches or with transistors in clock buffers. Broken points in the scan chain may then be determined based on the locations of unexpected light emission.

    摘要翻译: 提供了一种基于泄漏光发射来诊断断层扫描链的机构。 图像捕获机构检测互补金属氧化物半导体(CMOS)器件中的泄漏电流的发光。 诊断机制识别具有意外发光的设备。 意外的发光量可能表明当它应该被打开时晶体管被关闭,反之亦然。 可以测试所有可能的输入以确定锁存器中的晶体管或时钟缓冲器中的晶体管是否存在问题。 然后可以基于意外光发射的位置来确定扫描链中的断点。

    Enhanced signal observability for circuit analysis

    公开(公告)号:US07355419B2

    公开(公告)日:2008-04-08

    申请号:US10912493

    申请日:2004-08-05

    IPC分类号: G01R31/302

    CPC分类号: G01R31/311

    摘要: Methods and arrangements to enhance photon emissions responsive to a signal within an integrated circuit (IC) for observability of signal states utilizing, e.g., picosecond imaging circuit analysis (PICA), are disclosed. Embodiments attach a beacon to the signal of interest and apply a voltage across the beacon to enhance photon emissions responsive to the signal of interest. The voltage is greater than the operable circuit voltage, Vdd, to enhance photon emissions with respect to intensity and energy. Thus, the photon emissions are more distinguishable from noise. In many embodiments, the beacon includes a transistor and, in several embodiments, the beacon includes an enablement device to enable and disable photon emissions from the beacon. Further, a PICA detector may capture photon emissions from the beacon and process the photons to generate time traces.

    Constructing variability maps by correlating off-state leakage emission images to layout information
    5.
    发明授权
    Constructing variability maps by correlating off-state leakage emission images to layout information 失效
    通过将非状态泄漏图像与布局信息相关联来构建变异性图

    公开(公告)号:US08131056B2

    公开(公告)日:2012-03-06

    申请号:US12241926

    申请日:2008-09-30

    IPC分类号: G06K9/00

    CPC分类号: G06T7/001 G06T2207/30148

    摘要: Improved techniques are disclosed for monitoring or sensing process variations in integrated circuit designs. Such techniques provide such improvements by constructing variability maps correlating leakage emission images to layout information. By way of example, a method for monitoring one or more manufacturing process variations associated with a device under test (e.g., integrated circuit) comprises the following steps. An emission image representing an energy emission associated with a leakage current of the device under test is obtained. The emission image is correlated with a layout of the device under test to form a cross emission image. Common structures on the cross emission image are selected and identified as regions of interest. One or more variability measures (e.g., figures of merit) are calculated based on the energy emissions associated with the regions of interest. A variability map is created based on the calculated variability measures, wherein the variability map is useable to monitor the one or more manufacturing process variations associated with the device under test.

    摘要翻译: 公开了用于监测或感测集成电路设计中的工艺变化的改进的技术。 这样的技术通过构建将泄漏发射图像与布局信息相关联的可变性图来提供这样的改进。 作为示例,用于监测与被测器件(例如,集成电路)相关联的一个或多个制造工艺变化的方法包括以下步骤。 获得表示与被测设备的泄漏电流相关联的能量发射的发射图像。 发射图像与待测器件的布局相关,以形成交叉发射图像。 选择交叉发射图像上的共同结构并将其识别为感兴趣的区域。 基于与感兴趣区域相关联的能量排放来计算一个或多个可变性度量(例如,品质因素)。 基于所计算的变异性度量创建变异性图,其中可变性图可用于监测与被测设备相关联的一个或多个制造过程变化。

    Enhanced signal observability for circuit analysis
    6.
    发明授权
    Enhanced signal observability for circuit analysis 有权
    电路分析增强的信号可观测性

    公开(公告)号:US07446550B2

    公开(公告)日:2008-11-04

    申请号:US11949325

    申请日:2007-12-03

    IPC分类号: G01R31/02

    CPC分类号: G01R31/311

    摘要: Methods and arrangements to enhance photon emissions responsive to a signal within an integrated circuit (IC) for observability of signal states utilizing, e.g., picosecond imaging circuit analysis (PICA), are disclosed. Embodiments attach a beacon to the signal of interest and apply a voltage across the beacon to enhance photon emissions responsive to the signal of interest. The voltage is greater than the operable circuit voltage, Vdd, to enhance photon emissions with respect to intensity and energy. Thus, the photon emissions are more distinguishable from noise. In many embodiments, the beacon includes a transistor and, in several embodiments, the beacon includes an enablement device to enable and disable photon emissions from the beacon. Further, a PICA detector may capture photon emissions from the beacon and process the photons to generate time traces.

    摘要翻译: 公开了利用例如皮秒成像电路分析(PICA)来增强响应于集成电路(IC)内的信号的信号状态的可观察性的光子发射的方法和装置。 实施例将信标连接到感兴趣的信号,并在信标之间施加电压以增强响应于感兴趣的信号的光子发射。 电压大于可操作电路电压Vdd,以增强相对于强度和能量的光子发射。 因此,光子发射与噪声更为区别。 在许多实施例中,信标包括晶体管,并且在几个实施例中,信标包括启用和禁用来自信标的光子发射的启用装置。 此外,PICA检测器可以捕获来自信标的光子发射并处理光子以产生时间迹线。

    Constructing Variability Maps by Correlating Off-State Leakage Emission Images to Layout Information
    7.
    发明申请
    Constructing Variability Maps by Correlating Off-State Leakage Emission Images to Layout Information 失效
    通过将非状态泄漏图像关联到布局信息来构建变异图

    公开(公告)号:US20100080445A1

    公开(公告)日:2010-04-01

    申请号:US12241926

    申请日:2008-09-30

    IPC分类号: G06K9/00

    CPC分类号: G06T7/001 G06T2207/30148

    摘要: Improved techniques are disclosed for monitoring or sensing process variations in integrated circuit designs. Such techniques provide such improvements by constructing variability maps correlating leakage emission images to layout information. By way of example, a method for monitoring one or more manufacturing process variations associated with a device under test (e.g., integrated circuit) comprises the following steps. An emission image representing an energy emission associated with a leakage current of the device under test is obtained. The emission image is correlated with a layout of the device under test to form a cross emission image. Common structures on the cross emission image are selected and identified as regions of interest. One or more variability measures (e.g., figures of merit) are calculated based on the energy emissions associated with the regions of interest. A variability map is created based on the calculated variability measures, wherein the variability map is useable to monitor the one or more manufacturing process variations associated with the device under test.

    摘要翻译: 公开了用于监测或感测集成电路设计中的工艺变化的改进的技术。 这样的技术通过构建将泄漏发射图像与布局信息相关联的可变性图来提供这样的改进。 作为示例,用于监测与被测器件(例如,集成电路)相关联的一个或多个制造工艺变化的方法包括以下步骤。 获得表示与被测设备的泄漏电流相关联的能量发射的发射图像。 发射图像与待测器件的布局相关,以形成交叉发射图像。 选择交叉发射图像上的共同结构并将其识别为感兴趣的区域。 基于与感兴趣区域相关联的能量排放来计算一个或多个可变性度量(例如,品质因素)。 基于所计算的变异性度量创建变异性图,其中可变性图可用于监测与被测设备相关联的一个或多个制造过程变化。

    Analysis methods of leakage current luminescence in CMOS circuits
    8.
    发明授权
    Analysis methods of leakage current luminescence in CMOS circuits 失效
    CMOS电路中漏电流发光的分析方法

    公开(公告)号:US06909295B2

    公开(公告)日:2005-06-21

    申请号:US10669305

    申请日:2003-09-24

    CPC分类号: G01R31/025 G01R31/2621

    摘要: Disclosed are a method and system for analyzing leakage current luminescence in CMOS circuits. The method comprises the steps of collecting light emission data from each of a plurality of CMOS circuits, and separating the CMOS circuits into first and second groups. For the first group of CMOS circuits, the emission data from the CMOS circuits are analyzed, based on the presence or absence of leakage light from the CMOS circuits, to identify logic states for the CMOS circuits. For the second group of CMOS circuits, the emission data from the CMOS circuits are analyzed, based on modulation of the intensity of the light from the CMOS circuits, to determine values for given parameters of the circuits. These parameters may be, for example, temperature, cross-talk or power distribution noise.

    摘要翻译: 公开了一种用于分析CMOS电路中的漏电流发光的方法和系统。 该方法包括以下步骤:从多个CMOS电路中的每一个收集发光数据,并将CMOS电路分离成第一和第二组。 对于第一组CMOS电路,基于来自CMOS电路的泄漏光的存在或不存在来分析来自CMOS电路的发射数据,以识别CMOS电路的逻辑状态。 对于第二组CMOS电路,基于来自CMOS电路的光的强度的调制来分析来自CMOS电路的发射数据,以确定电路的给定参数的值。 这些参数可以是例如温度,串扰或功率分配噪声。

    Minimum-spacing circuit design and layout for PICA
    9.
    发明授权
    Minimum-spacing circuit design and layout for PICA 有权
    PICA的最小间距电路设计和布局

    公开(公告)号:US09229044B2

    公开(公告)日:2016-01-05

    申请号:US13463166

    申请日:2012-05-03

    摘要: PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

    摘要翻译: 示出了PICA测试方法,其包括形成具有近端发光区域的半导体器件,使得发光区域被分组成由目标分辨率尺寸所控制的距离分开的不同形状; 形成逻辑电路以控制半导体器件; 通过提供输入信号来激活所述一个或多个半导体器件; 并且通过向逻辑电路提供一个或多个选择信号来抑制来自一个或多个激活的半导体器件的光发射。

    MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA
    10.
    发明申请
    MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA 审中-公开
    PICA的最小间距电路设计和布局

    公开(公告)号:US20130280828A1

    公开(公告)日:2013-10-24

    申请号:US13463166

    申请日:2012-05-03

    IPC分类号: H01L21/66

    摘要: PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

    摘要翻译: 示出了PICA测试方法,其包括形成具有近端发光区域的半导体器件,使得发光区域被分组成由目标分辨率尺寸所控制的距离分开的不同形状; 形成逻辑电路以控制半导体器件; 通过提供输入信号来激活所述一个或多个半导体器件; 并且通过向逻辑电路提供一个或多个选择信号来抑制来自一个或多个激活的半导体器件的光发射。