公开(公告)号：US20160170877A1

公开(公告)日：2016-06-16

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： GEORGE PATSILARAS ,  BOHUSLAV RYCHLIK ,  ANDREW EDMUND TURNER ,  KRIS TIRI ,  JEONG-HO WOO ,  ANWAR ROHILLAH ,  FENG WANG ,  MOINUL KHAN ,  SUBBARAO PALACHARLA

IPC: G06F12/08 ,  G06F13/16 ,  G06F9/46 ,  G06F1/32

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US20210049099A1

公开(公告)日：2021-02-18

申请号：US16543328

申请日：2019-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： ANDREW EDMUND TURNER ,  George PATSILARAS ,  Bohuslav RYCHLIK ,  Wesley James HOLLAND ,  Jeffrey SHABEL ,  Simon Peter William BOOTH

IPC: G06F12/0846 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/121

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.