公开(公告)号：US20160170877A1

公开(公告)日：2016-06-16

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： GEORGE PATSILARAS ,  BOHUSLAV RYCHLIK ,  ANDREW EDMUND TURNER ,  KRIS TIRI ,  JEONG-HO WOO ,  ANWAR ROHILLAH ,  FENG WANG ,  MOINUL KHAN ,  SUBBARAO PALACHARLA

IPC: G06F12/08 ,  G06F13/16 ,  G06F9/46 ,  G06F1/32

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US20150302903A1

公开(公告)日：2015-10-22

申请号：US14257980

申请日：2014-04-21

Applicant: QUALCOMM INCORPORATED

Inventor： PANKAJ CHAURASIA ,  MOINUL KHAN ,  VINOD CHAMARTY ,  SUBBARAO PALACHARLA ,  DEXTER CHUN

IPC: G11C7/10 ,  G06F12/08

CPC classification number: G11C7/1072 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F2212/1024 ,  G06F2212/171

Abstract: Various embodiments of methods and systems for deep coalescing memory management (“DCMM”) in a portable computing device (“PCD”) are disclosed. Because multiple active multimedia (“MM”) clients running on the PCD may generate a random stream of mixed read and write requests associated with data stored at non-contiguous addresses in a double data rate (“DDR”) memory component, DCMM solutions triage the requests into dedicated deep coalescing (“DC”) cache buffers, sequentially ordering the requests and/or the DC buffers based on associated addresses for the data in the DDR, to optimize read and write transactions from and to the DDR memory component in blocks of contiguous data addresses.

Abstract translation: 公开了便携式计算设备（“PCD”）中深层聚合存储器管理（“DCMM”）的方法和系统的各种实施例。 由于在PCD上运行的多个活动多媒体（“MM”）客户端可以生成与双数据速率（“DDR”）存储器组件中存储在非连续地址中的数据相关联的混合读和写请求的随机流，DCMM解决方案 请求进入专用深度合并（“DC”）高速缓冲存储器，根据DDR中的数据的相关地址顺序排序请求和/或DC缓冲区，以优化块内的DDR存储器组件的读写事务 的连续数据地址。

公开(公告)号：US20170116118A1

公开(公告)日：2017-04-27

申请号：US14921468

申请日：2015-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： ALAIN ARTIERI ,  SUBBARAO PALACHARLA ,  LAURENT MOLL ,  RAGHU SANKURATRI ,  Kedar Bhloe ,  Vinod Chamarty

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.