公开(公告)号：US20210173808A1

公开(公告)日：2021-06-10

申请号：US16703720

申请日：2019-12-04

Applicant: QUALCOMM Incorporated

Inventor： Subramanian Kizhakkenchery ANANTHANARAYANAN ,  Joy CHAKRABORTY ,  Arun GOTHEKAR

IPC: G06F13/42 ,  G06F13/40 ,  G06F11/10 ,  G06F11/07 ,  G06F9/46

Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A method for managing transactions executed on a serial bus includes configuring a slave device coupled to the serial bus with information identifying a first number to be used to count data bytes, initiating a first transaction to transmit a block of data that has a second number of data bytes to the slave device, the second number being greater than the first number, and providing an opportunity for the slave device to acknowledge receipt of an immediately preceding first number of data bytes after an integer multiple of the first number of data bytes has been transmitted.

公开(公告)号：US20250103092A1

公开(公告)日：2025-03-27

申请号：US18476111

申请日：2023-09-27

Applicant: QUALCOMM INCORPORATED

Inventor： Prashanth Kumar KAKKIRENI ,  Naveen Kumar NARALA ,  Amod PHADKE ,  Arun GOTHEKAR ,  Anirudh GHAYAL

IPC: G06F1/10 ,  G06F1/3287 ,  G06F15/78

Abstract: A global count or reference time in a computing device may be maintained during a sleep state in which the global counter is powered off. The global count from the global counter may be saved in a register when the sleep state is entered. When the sleep state is exited, the global count in the register may be restored in the global counter.

公开(公告)号：US20240113986A1

公开(公告)日：2024-04-04

申请号：US17937495

申请日：2022-10-03

Applicant: QUALCOMM Incorporated

Inventor： Narasimha Rao KORAMUTLA ,  Arun GOTHEKAR ,  Susheel Kumar Yadav YADAGIRI ,  Akshat GUPTA ,  Srinivas MARAKALA ,  Naveen Kumar NARALA ,  Radvajesh MUNIBYRAIAH

IPC: H04L47/62 ,  H04L47/2416 ,  H04L47/28 ,  H04L65/65 ,  H04L69/22

CPC classification number: H04L47/624 ,  H04L47/2416 ,  H04L47/28 ,  H04L65/65 ,  H04L69/22

Abstract: Various embodiments include an automobile network device that includes a descriptor sorting engine (DSE). The DSE may include a direct memory access (DMA) controller, a memory organized by channel clusters that each include a plurality of first-in first-out (FIFO) memories, a timer, and a time stamp (TS) sorting logic component. The DMA controller may be configured to pull timestamp-pointer pairs from packet descriptors stored in an unsorted descriptor ring memory, store the timestamp-pointer pairs in the FIFO memories, trigger the TS sorting logic component to reorder the timestamp-pointer pairs in the FIFO memories so that they are sorted in ascending order, use the sorted timestamp-pointer pairs in the FIFO memories to read the packet descriptors stored in an unsorted descriptor ring memory, and store the packet descriptors in a sorted descriptor ring memory.

公开(公告)号：US20210141757A1

公开(公告)日：2021-05-13

申请号：US16681380

申请日：2019-11-12

Applicant: QUALCOMM Incorporated

Inventor： Joy CHAKRABORTY ,  Subramanian Kizhakkenchery ANANTHANARAYANAN ,  Arun GOTHEKAR

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/16 ,  G06F1/324

Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A method for bus arbitration includes determining that at least one device coupled to a serial bus has been assigned a dynamic address with a non-zero most significant address bit, determining that all devices coupled to the serial bus have been assigned dynamic addresses that have a common zero-value address bit, initiating transmission of an arbitrable address header while a line driver coupled to a data line of the serial bus is configured for an open-drain mode of operation, and configuring the line driver coupled to the data line for a push-pull mode of operation when a bit in the arbitrable address header corresponding to the common zero-value address bit has a non-zero value on the data line. In one example, the serial bus may be operated in accordance with an I3C protocol.