公开(公告)号：US20190006001A1

公开(公告)日：2019-01-03

申请号：US15636565

申请日：2017-06-28

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER CHUN ,  Yanru Li

IPC: G11C11/406

Abstract: Systems and methods are disclosed for error correction control (ECC) for a refreshable memory device coupled to a system on a chip SoC. The memory device including a parity region and a user data region. A method includes determining with the SoC a first refresh rate for the user data region of the memory device and a second refresh rate for the parity region of the memory device, where the second refresh rate is different than the first refresh rate. Parity data is generated for a write operation of a user payload data (UPD) to the user data region of the memory device. The user data region of the memory device is refreshed at the first refresh rate and the parity region is refreshed at the second refresh rate.

公开(公告)号：US20170371595A1

公开(公告)日：2017-12-28

申请号：US15191400

申请日：2016-06-23

Applicant: QUALCOMM INCORPORATED

Inventor： SUBRATO KUMAR DE ,  DEXTER CHUN ,  YANRU LI

IPC: G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for scheduling decompression of an application from flash storage. One embodiment of a system comprises a flash memory device and a preemptive decompression scheduler component. The preemptive decompression scheduler component comprises logic configured to generate and store metadata defining one or more dependent objects associated with the compressed application in response to an application installer component installing a compressed application to the flash memory device. In response to a launch of the compressed application by an application launcher component, the preemptive decompression scheduler component determines from the stored metadata the one or more dependent objects associated with the compressed application to be launched. The preemptive decompression scheduler component preemptively schedules decompression of the one or more dependent objects based on the stored metadata.

公开(公告)号：US20180286473A1

公开(公告)日：2018-10-04

申请号：US15472622

申请日：2017-03-29

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER CHUN ,  YANRU LI

IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program to fill an allocated portion of the DRAM with a predetermined pattern of values. The predetermined pattern of values is stored in a fill value memory residing in the DRAM. A fill command is sent to the DRAM. In response to the fill command, a plurality of sense amp latches are connected to the fill value memory to update the corresponding sense amp latch bits with the predetermined pattern of values stored in the fill value memory.

公开(公告)号：US20150134989A1

公开(公告)日：2015-05-14

申请号：US14079620

申请日：2013-11-13

Applicant: Qualcomm Incorporated

Inventor： DEXTER CHUN ,  HAW-JING LO

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3253 ,  G06F7/764 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4096

Abstract: Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.

Abstract translation: 公开了用于降低存储器I / O功率的系统和方法。 一个实施例是包括片上系统（SoC），DRAM存储器件和数据屏蔽功率降低模块的系统。 SoC包括一个内存控制器。 DRAM存储器件通过多个DQ引脚耦合到存储器控制器。 数据屏蔽功率降低模块包括被配置为在数据屏蔽操作期间将DQ引脚驱动到功率节省状态的逻辑。

公开(公告)号：US20150121096A1

公开(公告)日：2015-04-30

申请号：US14062859

申请日：2013-10-24

Applicant: Qualcomm Incorporated

Inventor： DEXTER CHUN ,  HAW-JING LO

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  H03M7/40 ,  H03M7/6047

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.

Abstract translation: 公开了用于节省存储器系统中的功耗的系统和方法。 一种这样的系统包括片上系统（SoC）和编码器。 SoC包括用于访问耦合到SoC的动态随机存取存储器（DRAM）存储器系统的一个或多个存储器客户端。 编码器驻留在SoC上，并且被配置为通过根据压缩方案对接收的存储器数据进行编码来减少从存储器客户机接收的存储器数据的数据活动因子，并将编码的存储器数据提供给DRAM存储器系统。 DRAM存储器系统被配置为根据压缩方案将经编码的存储器数据解码为接收的存储器数据。

公开(公告)号：US20150089112A1

公开(公告)日：2015-03-26

申请号：US14033233

申请日：2013-09-20

Applicant: Qualcomm Incorporated

Inventor： HAW-JING LO ,  DEXTER CHUN

IPC: G06F13/40 ,  G06F1/32 ,  G06F13/16

CPC classification number: G06F13/4018 ,  G06F1/3253 ,  G06F1/3275 ,  G06F13/1678 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

Abstract translation: 公开了用于节省存储器系统中的功耗的系统和方法。 一种这样的系统包括DRAM存储器系统和片上系统（SoC）。 SoC通过存储器总线耦合到DRAM存储器系统。 SoC包括用于处理来自一个或多个存储器客户端的访问DRAM存储器系统的存储器请求的一个或多个存储器控制器。 一个或多个存储器控制器被配置为通过动态地调整存储器总线的总线宽度来选择性地节省存储器功耗。

公开(公告)号：US20180373314A1

公开(公告)日：2018-12-27

申请号：US15634956

申请日：2017-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD STEWART ,  DEXTER CHUN

IPC: G06F1/32 ,  G06F13/16 ,  G06F13/40

Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.

公开(公告)号：US20180335828A1

公开(公告)日：2018-11-22

申请号：US15600318

申请日：2017-05-19

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER CHUN ,  RICHARD STEWART

IPC: G06F1/32

CPC classification number: G06F13/1689 ,  G06F1/3234 ,  G06F1/3253

Abstract: Systems and methods are disclosed for reducing double data rate (DDR) memory power consumption via device-specific customization of DDR interface parameters. One embodiment comprises a method for minimizing double data rate (DDR) power consumption. The method selects one of a plurality of operating points for a DDR interface electrically coupling a DDR memory to a memory controller residing on a system on chip (SoC). The memory controller executes a memory test via the DDR interface at the selected operating point. During the execution of the memory test at the selected operating point, the method determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.

公开(公告)号：US20180189195A1

公开(公告)日：2018-07-05

申请号：US15399625

申请日：2017-01-05

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER CHUN ,  YANRU LI

IPC: G06F12/14 ,  G06F21/60

CPC classification number: G06F12/1425 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052

Abstract: Systems and methods are disclosed for providing secure access to a non-volatile random access memory. One such method comprises sending an unlock password to a non-volatile random access memory (NVRAM) in response to a trusted boot program executing on a system on chip (SoC). The NVRAM compares the unlock password to a pass gate value provisioned in the NVRAM. If the unlock password matches the pass gate value, a pass gate is unlocked to enable the SoC to access a non-volatile cell array in the NVRAM.

公开(公告)号：US20170371593A1

公开(公告)日：2017-12-28

申请号：US15191399

申请日：2016-06-23

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER CHUN

IPC: G06F3/06 ,  G06F17/30

CPC classification number: G06F3/0661 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F16/1744 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7204

Abstract: Systems, methods, and computer programs are disclosed for selectively compressing/decompressing flash storage data. An embodiment of a system comprises a compression/decompression component, a flash memory device, a flash controller in communication with the flash memory device, and a storage driver in communication with the compression/decompression component and the flash controller. The storage driver is configured to selectively control compression and decompression of data stored in the flash memory device, via the compression/decompression component, according to a storage usage collar comprising an upper usage threshold and a lower usage threshold.