公开(公告)号：US11296700B1

公开(公告)日：2022-04-05

申请号：US17065382

申请日：2020-10-07

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Renaud Francois Henri Gelin

IPC: H03K19/003 ,  H03K3/013 ,  G06F11/18

Abstract: A triple modular redundancy (TMR) flip-flop includes a set of master-gate-latch circuits including a first set of inputs to receive a first digital signal, and a second set of inputs to receive a clock; and a voting logic circuit including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal. Another TMR flip-flop includes a set of master-gate-latch circuits to receive a set of digital signals in response to a first edge of a clock, respectively; and latch the set of digital signals in response to a second edge of the clock, respectively; and a voting logic circuit to receive the latched set of digital signals; and generate a second digital signal based on a majority of logic levels of the latched first set of digital signals, respectively.

公开(公告)号：US20180300107A1

公开(公告)日：2018-10-18

申请号：US15488019

申请日：2017-04-14

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao

IPC: G06F7/502 ,  G06F7/505

CPC classification number: G06F7/502 ,  G06F7/505 ,  G06F7/506 ,  G06F2207/5063

Abstract: A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate (PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs.

公开(公告)号：US20140247825A1

公开(公告)日：2014-09-04

申请号：US13781755

申请日：2013-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： Hari Rao ,  Ioannis Nousias ,  Sami Khawam

IPC: H04Q11/00

CPC classification number: H04Q11/00 ,  H03K19/1737

Abstract: An output switch fabric is disclosed that comprises an interleaved plurality of multiplexers for switching channels between first and second busses. The busses run in tracks that form a grid pattern. The interleaving of the multiplexers is arranged according to the grid pattern for the busses.

Abstract translation: 公开了一种输出交换结构，其包括用于在第一和第二总线之间切换信道的交错多个多路复用器。 总线在形成网格图案的轨道中运行。 多路复用器的交错是根据总线的网格图案来布置的。

公开(公告)号：US20150100842A1

公开(公告)日：2015-04-09

申请号：US14046084

申请日：2013-10-04

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli ,  Sagar Suresh Sabade ,  Bilal Zafar

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract translation: 提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。 主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有 用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。

公开(公告)号：US20150074324A1

公开(公告)日：2015-03-12

申请号：US14025646

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Ioannis Nousias ,  Sami Khawam

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F1/08 ,  G06F1/1615 ,  G06F12/125 ,  G06F15/80 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract translation: 可重构指令单元阵列（RICA）包括多个开关盒。 每个开关盒包括根据存储在每个开关盒中的配置字可配置的指令单元和交换结构。 开关盒被布置成串行加载组，使得每个串行加载组中的开关盒被配置为形成用于串行移位相应配置字的多位移位寄存器链。

公开(公告)号：US10223071B2

公开(公告)日：2019-03-05

申请号：US15488019

申请日：2017-04-14

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao

IPC: G06F7/502 ,  G06F7/505 ,  G06F7/506

Abstract: A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate (PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs.

公开(公告)号：US09210486B2

公开(公告)日：2015-12-08

申请号：US13781755

申请日：2013-03-01

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Ioannis Nousias ,  Sami Khawam

IPC: H04Q11/00 ,  H03K19/173

CPC classification number: H04Q11/00 ,  H03K19/1737

Abstract: An output switch fabric is disclosed that comprises an interleaved plurality of multiplexers for switching channels between first and second busses. The busses run in tracks that form a grid pattern. The interleaving of the multiplexers is arranged according to the grid pattern for the busses.

Abstract translation: 公开了一种输出交换结构，其包括用于在第一和第二总线之间切换信道的交错多个多路复用器。 总线在形成网格图案的轨道中运行。 多路复用器的交错是根据总线的网格图案来布置的。

公开(公告)号：US09196341B2

公开(公告)日：2015-11-24

申请号：US14246169

申请日：2014-04-07

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Hari Rao

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  G06F17/50

CPC classification number: G11C11/1675 ,  G06F17/5068 ,  G11C11/1659 ,  G11C11/2255 ,  G11C11/2297 ,  G11C29/08 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A memory device having a local current sink is disclosed. In a particular embodiment, an electronic device is disclosed. The electronic device includes one or more write drivers. The electronic device includes at least one Magnetic Tunnel Junction (MTJ) coupled to a bit line and coupled to a source line. The electronic device also includes a current sink circuit comprising a single transistor, the single transistor coupled to the bit line and to the source line.

Abstract translation: 公开了一种具有局部电流吸收器的存储器件。 在特定实施例中，公开了一种电子设备。 电子设备包括一个或多个写入驱动器。 电子设备包括耦合到位线并耦合到源极线的至少一个磁隧道结（MTJ）。 电子设备还包括电流吸收电路，其包括单个晶体管，单个晶体管耦合到位线和源极线。

公开(公告)号：US20140258678A1

公开(公告)日：2014-09-11

申请号：US13784827

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Hari Rao ,  Sami Khawam ,  Ioannis Nousias ,  Raghavan Thirumala

IPC: G06F15/80

CPC classification number: G06F15/80 ,  G06F15/7871

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Abstract translation: 可重构指令单元阵列（RICA）包括多个开关盒。 每个开关盒包括根据存储在开关盒的锁存器阵列中的配置字来配置的指令单元和交换结构。 开关盒被布置成广播组，使得每个广播组中的锁存器阵列并行地接收配置字。

公开(公告)号：US11387819B2

公开(公告)日：2022-07-12

申请号：US17118476

申请日：2020-12-10

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao

IPC: H03K3/3562 ,  H03K19/096 ,  H03K19/003 ,  H03K19/0185 ,  H03K3/037 ,  H03K17/62

Abstract: The disclosure relates to a latch including a first inverter with a first pair of field effect transistors (FETs) configured with a first channel width to length ratio (W/L), and a second inverter with a second pair of FETs configured with a second W/L different than the first W/L. Another latch includes first and second inverters; a first negative feedback circuit including first and second FETs coupled between first and second voltage rails, the input of the first inverter coupled between the first and second FETs, and the first and second FETs including gates coupled to an output of the first inverter; and a second negative feedback circuit including third and fourth FETs coupled between the first and second voltage rails, the input of the second inverter coupled between the third and fourth FETs, and the third and fourth FETs including gates coupled to an output of the second inverter.