公开(公告)号：US09330040B2

公开(公告)日：2016-05-03

申请号：US14025646

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Ioannis Nousias ,  Sami Khawam

IPC: G06F3/00 ,  G06F13/28 ,  G06F13/00 ,  G06F13/40 ,  G06F12/12 ,  G06F1/16 ,  G06F15/80 ,  G06F1/08 ,  H03K19/177

CPC classification number: G06F13/4022 ,  G06F1/08 ,  G06F1/1615 ,  G06F12/125 ,  G06F15/80 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract translation: 可重构指令单元阵列（RICA）包括多个开关盒。 每个开关盒包括根据存储在每个开关盒中的配置字来配置的指令单元和交换结构。 开关盒被布置成串行加载集合，使得每个串行加载集合中的开关盒被配置为形成用于串行移位相应配置字的多位移位寄存器链。

公开(公告)号：US20160004617A1

公开(公告)日：2016-01-07

申请号：US14323916

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Hari Madhava Rao ,  Joseph Weizhou Fang ,  Sami Khawam ,  Ioannis Nousias ,  Raju Macha ,  Ihab Abdelmuti ,  Venugopal Boynapalli

IPC: G06F11/22 ,  G06F13/40

CPC classification number: G06F11/2289 ,  G06F11/221 ,  G06F11/2221 ,  G06F11/263 ,  G06F13/4022

Abstract: An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals.

Abstract translation: 提供了包括瓦片阵列的指令单元阵列。 每个瓦片包括用于在多个输入通道和多个相应的输出通道之间切换的一组输入/输出（I / O）端口。 此外，每个瓦片包括指令单元，该指令单元包括多个专用逻辑门，用于产生从瓦片的输入通道中的选定的输入通道输出的指令单元。 每个I / O端口被配置为从瓦片的指令单元输出和输入通道中选择用于瓦片的剩余I / O端口以形成I / O端口的输出通道。 为了在阵列的自动测试模式生成（ATPG）期间防止组合循环，本文公开的指令单元阵列被配置在测试模式中，使得每个瓦片的I / O端口的至少一个子集阻止其任何输出通道 被形成为组合信号。

公开(公告)号：US09465758B2

公开(公告)日：2016-10-11

申请号：US13905032

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Ioannis Nousias ,  Sami Khawam ,  Mark Ian Roy Muir

IPC: G06F13/20 ,  G06F15/78

CPC classification number: G06F13/20 ,  G06F15/7867

Abstract: A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.

Abstract translation: 公开了一种可重构指令单元阵列，其包括开关盒阵列。 阵列中的每个开关盒包括一组I / O端口，其被配置为从阵列中的相邻开关盒接收多个输入通道。 在开关盒内，其中一个I / O端口有选择地从开关盒中的剩余I / O端口接收的输入通道中选择，以形成要驱动到阵列中相邻开关盒的多个输出通道。

公开(公告)号：US20150074324A1

公开(公告)日：2015-03-12

申请号：US14025646

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Ioannis Nousias ,  Sami Khawam

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F1/08 ,  G06F1/1615 ,  G06F12/125 ,  G06F15/80 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract translation: 可重构指令单元阵列（RICA）包括多个开关盒。 每个开关盒包括根据存储在每个开关盒中的配置字可配置的指令单元和交换结构。 开关盒被布置成串行加载组，使得每个串行加载组中的开关盒被配置为形成用于串行移位相应配置字的多位移位寄存器链。

公开(公告)号：US20140359174A1

公开(公告)日：2014-12-04

申请号：US13905032

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Ioannis Nousias ,  Sami Khawam ,  Mark Ian Roy Muir

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F15/7867

Abstract: A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.

Abstract translation: 公开了一种可重构指令单元阵列，其包括开关盒阵列。 阵列中的每个开关盒包括一组I / O端口，其被配置为从阵列中的相邻开关盒接收多个输入通道。 在开关盒内，其中一个I / O端口有选择地从开关盒中的剩余I / O端口接收的输入通道中选择，以形成要驱动到阵列中相邻开关盒的多个输出通道。

公开(公告)号：US08860457B2

公开(公告)日：2014-10-14

申请号：US13784827

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Sami Khawam ,  Ioannis Nousias ,  Raghavan Thirumala

IPC: H03K19/177 ,  G06F15/80

CPC classification number: G06F15/80 ,  G06F15/7871

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Abstract translation: 可重构指令单元阵列（RICA）包括多个开关盒。 每个开关盒包括根据存储在开关盒的锁存器阵列中的配置字来配置的指令单元和交换结构。 开关盒被布置成广播组，使得每个广播组中的锁存器阵列并行地接收配置字。

公开(公告)号：US09722614B2

公开(公告)日：2017-08-01

申请号：US14553754

申请日：2014-11-25

Applicant: Qualcomm Incorporated

Inventor： Mark Ian Roy Muir ,  Sami Khawam ,  Ioannis Nousias

IPC: G06F13/10 ,  H03K19/177 ,  H03K19/0175 ,  G06F12/02 ,  G06F13/24 ,  G06F15/78 ,  G06F9/38

CPC classification number: H03K19/17764 ,  G06F9/3897 ,  G06F12/023 ,  G06F13/24 ,  G06F15/7867 ,  G06F2212/20 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/1776

Abstract: A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate times write-enable inputs of configuration registers are disabled.

公开(公告)号：US09210486B2

公开(公告)日：2015-12-08

申请号：US13781755

申请日：2013-03-01

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Ioannis Nousias ,  Sami Khawam

IPC: H04Q11/00 ,  H03K19/173

CPC classification number: H04Q11/00 ,  H03K19/1737

Abstract: An output switch fabric is disclosed that comprises an interleaved plurality of multiplexers for switching channels between first and second busses. The busses run in tracks that form a grid pattern. The interleaving of the multiplexers is arranged according to the grid pattern for the busses.

Abstract translation: 公开了一种输出交换结构，其包括用于在第一和第二总线之间切换信道的交错多个多路复用器。 总线在形成网格图案的轨道中运行。 多路复用器的交错是根据总线的网格图案来布置的。

公开(公告)号：US20140258678A1

公开(公告)日：2014-09-11

申请号：US13784827

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Hari Rao ,  Sami Khawam ,  Ioannis Nousias ,  Raghavan Thirumala

IPC: G06F15/80

CPC classification number: G06F15/80 ,  G06F15/7871

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Abstract translation: 可重构指令单元阵列（RICA）包括多个开关盒。 每个开关盒包括根据存储在开关盒的锁存器阵列中的配置字来配置的指令单元和交换结构。 开关盒被布置成广播组，使得每个广播组中的锁存器阵列并行地接收配置字。

公开(公告)号：US11580654B2

公开(公告)日：2023-02-14

申请号：US16893081

申请日：2020-06-04

Applicant: QUALCOMM Incorporated

Inventor： James Wilson Nash ,  Kalin Mitkov Atanassov ,  Ioannis Nousias ,  Mark Ian Roy Muir ,  Sami Khawam

IPC: G06T7/521 ,  G06V20/13 ,  G06V20/64

Abstract: Aspects of the present disclosure relate to systems and methods for active depth sensing. An example apparatus configured to perform active depth sensing includes a projector. The projector is configured to emit a first distribution of light during a first time and emit a second distribution of light different from the first distribution of light during a second time. A set of final depth values of one or more objects in a scene is based on one or more reflections of the first distribution of light and one or more reflections of the second distribution of light. The projector may include a laser array, and the apparatus may be configured to switch between a first plurality of lasers of the laser array to emit light during the first time and a second plurality of laser to emit light during the second time.