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    Runtime optimization of multi-core system designs for increased operating life and maximized performance
    1.
    发明授权
    Runtime optimization of multi-core system designs for increased operating life and maximized performance 有权

    公开(公告)号：US09606843B2

    公开(公告)日：2017-03-28

    申请号：US14166984

    申请日：2014-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Jon James Anderson ,  Richard Alan Stewart

    IPC: G06F9/45 ,  G06F9/50

    CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5066 ,  G06F9/5077

    Abstract: Aspects include computing devices, systems, and methods for adjusting the assignment of tasks to processor cores in a multi-core processing system to increase operating life and maximize device performance by wear-leveling the processor cores. A reliability engine may be configured to collect operation or built in self test data of thermal output and current leakage, and historical operation time for a group of equivalent processor cores configured for the same purpose. Collected data may be applied to a weighted function to determine priorities for each equivalent processor core in the group. The reliability engine may rearrange a virtual processor identification translation table according to the priorities of the equivalent processor cores. A high level operating system may issue a process request specifying a processor core and the specified processor core may be translated to a different processor core according to the order of processor cores dictated by the priorities.

    Runtime Optimization of Multi-core System Designs for Increased Operating Life and Maximized Performance
    2.
    发明申请
    Runtime Optimization of Multi-core System Designs for Increased Operating Life and Maximized Performance 有权
    多核系统设计的运行时优化，提高运行寿命和最大化性能

    公开(公告)号：US20150169382A1

    公开(公告)日：2015-06-18

    申请号：US14166984

    申请日：2014-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Jon James Anderson ,  Richard Alan Stewart

    IPC: G06F9/50

    CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5066 ,  G06F9/5077

    Abstract: Aspects include computing devices, systems, and methods for adjusting the assignment of tasks to processor cores in a multi-core processing system to increase operating life and maximize device performance by wear-leveling the processor cores. A reliability engine may be configured to collect operation or built in self test data of thermal output and current leakage, and historical operation time for a group of equivalent processor cores configured for the same purpose. Collected data may be applied to a weighted function to determine priorities for each equivalent processor core in the group. The reliability engine may rearrange a virtual processor identification translation table according to the priorities of the equivalent processor cores. A high level operating system may issue a process request specifying a processor core and the specified processor core may be translated to a different processor core according to the order of processor cores dictated by the priorities.

    Abstract translation: 方面包括用于在多核处理系统中调整任务分配给处理器核心的计算设备，系统和方法，以通过磨损均衡处理器核来增加操作寿命并最大化设备性能。 可靠性引擎可以被配置为收集热输出和电流泄漏的操作或内置的自测数据，以及为相同目的配置的一组等效处理器核的历史操作时间。 收集的数据可以应用于加权函数以确定组中每个等效处理器核心的优先级。 可靠性引擎可以根据等效处理器核心的优先级重新排列虚拟处理器识别转换表。 高级操作系统可以发出指定处理器核心的处理请求，并且指定的处理器核心可以根据由优先级决定的处理器核心的顺序被转换到不同的处理器核心。

    Dynamic mapping of applications on NVRAM/DRAM hybrid memory
    7.
    发明授权
    Dynamic mapping of applications on NVRAM/DRAM hybrid memory 有权

    公开(公告)号：US10338837B1

    公开(公告)日：2019-07-02

    申请号：US15946600

    申请日：2018-04-05

    Applicant: QUALCOMM Incorporated

    Inventor： Subrato Kumar De ,  Dexter Tamio Chun ,  Yanru Li ,  Bohuslav Rychlik ,  Richard Alan Stewart

    IPC: G06F3/06 ,  G06N20/00

    Abstract: This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.

    Efficient Decompression Locality System for Demand Paging
    9.
    发明申请
    Efficient Decompression Locality System for Demand Paging 有权
    有效的解压缩位置系统用于需求分页

    公开(公告)号：US20160124659A1

    公开(公告)日：2016-05-05

    申请号：US14526850

    申请日：2014-10-29

    Applicant: QUALCOMM Incorporated

    Inventor： Andres Alejandro Oportus Valenzuela ,  Richard Senior ,  Raghuveer Raghavendra ,  Nieyan Geng ,  Gurvinder Singh Chhabra ,  Richard Alan Stewart

    IPC: G06F3/06

    CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0673 ,  G06F12/08 ,  G06F2212/401 ,  H03M7/30

    Abstract: Aspects include computing devices, systems, and methods for implementing executing decompression of a compressed page. A computing device may determine a decompression block belonging to a compressed page that contains a code instruction requested in a memory access request. Decompression blocks, other than the decompression block containing the requested code instruction, may be selected for decompression based on their locality with respect to the decompression block containing the requested code instruction. Decompression blocks not identified for decompression may be substituted for a fault or exception code. The computing device may decompress decompression blocks identified for decompression, terminating the decompression of the compressed page upon filling all blocks with decompressed blocks, faults, or exception code. The remaining decompression blocks belonging to the compressed page may be decompressed after or concurrently with the execution of the requested code instruction.

    Abstract translation: 方面包括用于实现压缩页面的执行解压缩的计算设备，系统和方法。 计算设备可以确定属于压缩页面的解压缩块，其包含在存储器访问请求中请求的代码指令。 可以根据包含请求的代码指令的解压缩块的位置来选择解压缩块，除了包含请求的代码指令的解压缩块之外。 未被解压缩的解压缩块可以替代故障或异常代码。 计算设备可以解压缩被解压缩的解压缩块，在用解压缩块，故障或异常代码填充所有块时终止压缩页面的解压缩。 属于压缩页面的剩余解压缩块可以在执行所请求的代码指令之后或同时执行解压缩。

    System memory latency compensation
    10.
    发明授权
    System memory latency compensation 有权

    公开(公告)号：US10359803B2

    公开(公告)日：2019-07-23

    申请号：US15601924

    申请日：2017-05-22

    Applicant: QUALCOMM INCORPORATED

    Inventor： Dexter Tamio Chun ,  Richard Alan Stewart

    IPC: G06F1/32 ,  G06F1/08 ,  G06F3/06 ,  G06F1/3234 ,  G06F1/324 ,  G06F13/16

    Abstract: Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.

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