公开(公告)号：US20250140700A1

公开(公告)日：2025-05-01

申请号：US18494115

申请日：2023-10-25

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Hong Bok WE ,  Michelle Yejin KIM ,  Aniket PATIL ,  Yu-Ting HUANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/10

Abstract: In an aspect, a substrate for an integrated circuit (IC) package includes a first dielectric layer, a first metallization layer on a first surface of the first dielectric layer and including a first pad structure and a first trace structure, a second metallization layer on a second surface of the first dielectric layer and including a second pad structure and a second trace structure, a second dielectric layer on the second surface of the first dielectric layer, and a third metallization layer on a second surface of the second dielectric layer and having a third pad structure. The substrate further includes a conductive stud coupled to the second pad structure and a second via structure embedded in the second dielectric layer. The second via structure has a first end coupled to the conductive stud and a second end coupled to the third pad structure.

公开(公告)号：US20250070086A1

公开(公告)日：2025-02-27

申请号：US18455928

申请日：2023-08-25

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Joan Rey Villarba BUOT ,  Michelle Yejin KIM ,  Manuel ALDRETE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: A device includes a bottom substrate including first conductors, a top substrate including second conductors, and a first die disposed between the bottom substrate and the top substrate. The first die includes circuitry and first contacts electrically connected to the circuitry and to the first conductors. The device also includes a redistribution die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistribution die includes second contacts electrically connected to the first contacts through the first conductors and third contacts electrically connected to the second conductors. The redistribution die also includes redistribution traces electrically connected to the second contacts and to the third contacts. The top substrate includes fourth contacts electrically connected through the second conductors to the third contacts to define one or more signal paths between the fourth contacts and the first die.

公开(公告)号：US20240105568A1

公开(公告)日：2024-03-28

申请号：US17951601

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Hong Bok WE ,  Michelle Yejin KIM ,  Aniket PATIL

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2924/19041 ,  H01L2924/19042

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects located in the first dielectric layer, the second dielectric layer and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer.

公开(公告)号：US20230018448A1

公开(公告)日：2023-01-19

申请号：US17375676

申请日：2021-07-14

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Joan Rey Villarba BUOT ,  Hong Bok WE

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L27/108

Abstract: Disclosed are apparatus comprising a substrate and techniques for fabricating the same. The substrate may include a first metal layer having signal interconnects on a first side of the substrate. A second metal layer may include ground plane portions on a second side of the substrate. Conductive channels may be formed in the substrate and coupled to the ground plane portions. The conductive channels are configured to extend the ground plane portions towards the signal interconnects to reduce a distance from individual signal interconnects to individual conductive channels. The distance may be in a range of seventy-five percent to fifty percent of a substrate thickness between the first metal layer and the second metal layer.

公开(公告)号：US20220320016A1

公开(公告)日：2022-10-06

申请号：US17223947

申请日：2021-04-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Joan Rey Villarba BUOT

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/48 ,  H01L23/04 ,  H05K1/02

Abstract: In an aspect, an apparatus includes a package. The package includes a substrate, a plurality of components located on a top surface of the substrate, a plurality of ball pads located on a bottom surface of the substrate, a plurality of balls, and a plurality of test pads located on the bottom surface of the substrate. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads.

公开(公告)号：US20220246496A1

公开(公告)日：2022-08-04

申请号：US17164729

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Marcus HSU ,  Aniket PATIL

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US20220223529A1

公开(公告)日：2022-07-14

申请号：US17148367

申请日：2021-01-13

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Aniket PATIL ,  Zhijie WANG ,  Hong Bok WE

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: A package comprising a substrate comprising a plurality of interconnects, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, and an interconnect device coupled to the substrate. The first integrated device, the second integrated device, the interconnect device and the substrate are configured to provide an electrical path for an electrical signal between the first integrated device and the second integrated device, that extends through at least the substrate, through the interconnect device and back through the substrate. The electrical path includes at least one interconnect that extends diagonally.

公开(公告)号：US20210407919A1

公开(公告)日：2021-12-30

申请号：US16915199

申请日：2020-06-29

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Brigham NAVAJA

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Conventional package problems may be overcome with a hybrid metallization and laminate structure that avoids warpage problems and size reduction problems. One example structure may include a metallization structure directly attached to an active side of a logic die stack in a core substrate (on one or both sides of the substrate) with laminate layers built-up on top of the metallization structures for a symmetrical package structure.

公开(公告)号：US20210175178A1

公开(公告)日：2021-06-10

申请号：US16704378

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Aniket PATIL ,  Kuiwon KANG ,  Zhijie WANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A package comprising a first integrated device, a first encapsulation layer, a redistribution portion, a second integrated device and an encapsulation layer. The first encapsulation layer encapsulates the first integrated device. The redistribution portion includes a plurality of redistribution interconnects. The redistribution portion includes a first surface and a second surface. The first integrated device and the first encapsulation layer are coupled to the first surface of the redistribution portion. The second integrated device is coupled to the second surface of the redistribution portion. The second encapsulation layer is coupled to the second surface of the redistribution portion such that the second encapsulation layer encapsulates the second integrated device.

公开(公告)号：US20250132292A1

公开(公告)日：2025-04-24

申请号：US18491084

申请日：2023-10-20

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Joan Rey Villarba BUOT

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: A device includes a substrate that includes a first layer stack including multiple metal layers and multiple dielectric layers. A first metal layer includes contacts disposed in a first region and configured to electrically connect to a first IC device, via pads disposed in a second region, and traces electrically connected to the first contacts and to the via pads. One or more of the traces extend between a pair of the via pads. The substrate also includes a second layer stack disposed on the second region of the first metal layer. The second layer stack includes a dielectric layer and a second metal layer on the dielectric layer. The second metal layer defines second contacts configured to electrically connect to one or more second IC devices. The second layer stack also includes conductive vias extending between the via pads and the second contacts.