公开(公告)号：US20240243131A1

公开(公告)日：2024-07-18

申请号：US18098633

申请日：2023-01-18

Applicant: QUALCOMM Incorporated

Inventor： Ming-Huei LIN ,  Haining YANG ,  Junjing BAO

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/31155

Abstract: A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET further includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, on the first fin structure, and on the second fin structure. The metal gate is composed of a first sub-metal gate cut line filled with a first stressor material, and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

公开(公告)号：US20220262723A1

公开(公告)日：2022-08-18

申请号：US17176969

申请日：2021-02-16

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Haining YANG

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit (IC) having an interconnect structure with metal lines with different conductive materials for different widths and a method for fabricating such an IC. An example IC generally includes an active layer and an interconnect structure disposed thereabove and comprising a plurality of metal layers and one or more vias landing on metal lines. At least one of the plurality of metal layers comprises one or more first metal lines and one or more second metal lines. The one or more first metal lines have one or more first widths and comprise a first conductive material including copper. The one or more second metal lines have one or more second widths and comprise a second conductive material different from the first conductive material, where the second widths are narrower than the first widths. The vias have one or more third widths and comprise a third conductive material.

公开(公告)号：US20210280684A1

公开(公告)日：2021-09-09

申请号：US16812292

申请日：2020-03-07

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Haining YANG ,  Junjing BAO

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L29/66

Abstract: A gate all around transistor may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include a dielectric or air gap as an insulator between the channels of the transistors in the circuit. In another example, a transistor may include a first channel surrounded by a first metal, a second channel surrounded by a second metal proximate to the first channel, and an insulator, such as a dielectric or air gap, between the first metal and the second metal. The insulator helps reduce the parasitic capacitance between the source/drain regions and the metal fill regions of the transistor.

公开(公告)号：US20210020643A1

公开(公告)日：2021-01-21

申请号：US16511153

申请日：2019-07-15

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: Certain aspects of the present disclosure generally relate to a static random-access memory (SRAM) implemented using both a gate-all-around (GAA)-type transistor and a fin field-effect transistor (FinFET). For example, certain aspects are directed to an SRAM memory cell having a flip-flop (FF) having a pull-up (PU) transistor and a pull-down (PD) transistor, and a pass-gate (PG) transistor coupled between a bit line of the SRAM memory cell and the FF, a gate of the PG transistor being coupled to a word line (WL) of the SRAM memory cell. In certain aspects, at least one of the PU transistor, the PD transistor, or the PG transistor comprises a GAA transistor, and at least another one of the PU transistor, the PD transistor, or the PG transistor comprises a FinFET.

公开(公告)号：US20170040324A1

公开(公告)日：2017-02-09

申请号：US14817441

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Yanxiang LIU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7845

Abstract: A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.

Abstract translation: 根据这里的一些示例的finFET器件可以包括有源鳍元件上方的有源栅极元件和部分地断开有源栅极元件的虚设鳍元件。 在另一示例中，与有源栅极元件相邻的伪栅极元件包含部分地断开伪栅极元件的虚设鳍元件。 在另一个示例中，第一虚拟翅片元件部分地中断有源栅极元件，并且第二虚设鳍元件部分地断开伪栅极元件。 在另一个示例中，虚拟翅片元件具有与活动翅片元件相同的材料。 在另一个示例中，虚拟鳍片元件部分地打破栅极元件，但是不像活性鳍片元件那样延伸到衬底。

公开(公告)号：US20220336346A1

公开(公告)日：2022-10-20

申请号：US17234166

申请日：2021-04-19

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Haining YANG

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/552

Abstract: A metal oxide metal (MOM) capacitor and methods for fabricating the same are disclosed. The MOM capacitor includes a first metal layer having a first plurality of fingers, each of the first plurality of fingers configured to have alternating polarities. A high resistance (Hi-R) conductor layer is disposed adjacent the first metal layer in a plane parallel to the first metal layer.

公开(公告)号：US20220328237A1

公开(公告)日：2022-10-13

申请号：US17226744

申请日：2021-04-09

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Haining YANG

IPC: H01F27/29 ,  H01F17/00 ,  H01L49/02 ,  H01F41/04

Abstract: Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

公开(公告)号：US20210407998A1

公开(公告)日：2021-12-30

申请号：US16917451

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  ChihWei KUO ,  Junjing BAO

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: A transistor channel profile structure may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include different fin profiles for the NMOS transistors and the PMOS transistors, such as the NMOS fins are thicker than the PMOS fins or the NMOS fin has a straight vertical surface and the PMOS fin has a notch at a fin bottom region. In still another example, a transistor circuit may include different nano-sheet profiles for a NMOS GAA device and a PMOS GAA device where the NMOS nano-sheet is thicker than the PMOS nano-sheet. Such configurations optimize the NMOS and the PMOS transistors with the NMOS having a low channel resistance while the PMOS has a lower short channel effect.

公开(公告)号：US20210320175A1

公开(公告)日：2021-10-14

申请号：US16844699

申请日：2020-04-09

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  John Jianhong ZHU

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: The parasitic capacitance of a transistor may be reduced by mismatching the source and drain. Faster low finger count transistors may be achieved with lower drain capacitance and a frequency gain on the D1 inverter as described for the examples herein. In one such example, a transistor includes a source and a drain wherein a length of the source is more than a length of the drain, a width of the source is more than a width of the drain, or a height of the source is more than a height of the drain.

公开(公告)号：US20210183869A1

公开(公告)日：2021-06-17

申请号：US16712063

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Haining YANG ,  Bin YANG

IPC: H01L27/11 ,  H01L29/78 ,  G11C11/412 ,  H01L29/66

Abstract: Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.