公开(公告)号：US11327922B2

公开(公告)日：2022-05-10

申请号：US16997505

申请日：2020-08-19

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Sai Ganapathy Srinivasan ,  Navdeep Mer ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40 ,  G06F1/08

Abstract: The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.

公开(公告)号：US20240264962A1

公开(公告)日：2024-08-08

申请号：US18166171

申请日：2023-02-08

Applicant: QUALCOMM Incorporated

Inventor： Christopher Kong Yee Chun ,  John Fletcher ,  Sriharsha Chakka ,  Navdeep Mer ,  Sreenivasan Jouly Jothiram

IPC: G06F13/362 ,  G06F1/26

CPC classification number: G06F13/3625 ,  G06F1/266

Abstract: Systems and methods for bus clock line handover are disclosed. In one aspect, a clock line in a bus is driven continuously during bus handover without having contentious or contradictory drive signals being provided. After arbitration, an original bus master will drive the clock line to a predetermined value until detecting a state change on a data line. An incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the state change detected by the original bus master that causes the original bus master to stop driving the clock line.

公开(公告)号：US20220058153A1

公开(公告)日：2022-02-24

申请号：US16997505

申请日：2020-08-19

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Sai Ganapathy Srinivasan ,  Navdeep Mer ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40 ,  G06F1/08

Abstract: The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.

公开(公告)号：US20220019548A1

公开(公告)日：2022-01-20

申请号：US16931826

申请日：2020-07-17

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Amit Gil ,  Navdeep Mer ,  Viney Kumar

IPC: G06F13/362 ,  G06F13/24 ,  G06F13/40 ,  G06F9/54

Abstract: Nested commands for a radio frequency front end (RFFE) bus are provided. In particular, timing commands may be nested inside a normal data flow. On receipt of a nested timing command, a slave on the RFFE bus suspends or halts an active command and addresses the timing command. On completion of the timing command, the slave returns to the halted command. By allowing such nested commands, counters in the slave that would otherwise be used to track triggers may be eliminated or reduced and power may be conserved by placing a clock signal associated with the bus into a low power mode.

公开(公告)号：US12164460B2

公开(公告)日：2024-12-10

申请号：US17923110

申请日：2021-04-16

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Navdeep Mer ,  Naveen Kumar Narala ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. In one example, a method performed at a device coupled to a serial bus includes receiving a write command from the serial bus in a datagram, writing a data byte received in a first data frame of the datagram to a register address identified by the datagram, and using a second data frame of the datagram to provide feedback regarding the datagram. Feedback may be provided by driving a data line of the serial bus to provide a negative acknowledgement during the second data frame when a transmission error is detected in the datagram, and refraining from driving the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgement of the datagram.

公开(公告)号：US12130761B2

公开(公告)日：2024-10-29

申请号：US18166171

申请日：2023-02-08

Applicant: QUALCOMM Incorporated

Inventor： Christopher Kong Yee Chun ,  John Fletcher ,  Sriharsha Chakka ,  Navdeep Mer ,  Sreenivasan Jouly Jothiram

IPC: G06F13/362 ,  G06F1/26

CPC classification number: G06F13/3625 ,  G06F1/266

Abstract: Systems and methods for bus clock line handover are disclosed. In one aspect, a clock line in a bus is driven continuously during bus handover without having contentious or contradictory drive signals being provided. After arbitration, an original bus master will drive the clock line to a predetermined value until detecting a state change on a data line. An incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the state change detected by the original bus master that causes the original bus master to stop driving the clock line.

公开(公告)号：US11360916B2

公开(公告)日：2022-06-14

申请号：US17005143

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Navdeep Mer ,  Lior Amarilio

IPC: G06F13/16 ,  G06F1/28 ,  G06F13/42 ,  G06F13/40 ,  G06F11/07

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.

公开(公告)号：US11354266B2

公开(公告)日：2022-06-07

申请号：US16997542

申请日：2020-08-19

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Kishalay Haldar ,  Navdeep Mer ,  Viney Kumar ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/374

Abstract: The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

公开(公告)号：US20220058154A1

公开(公告)日：2022-02-24

申请号：US16997542

申请日：2020-08-19

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Kishalay Haldar ,  Navdeep Mer ,  Viney Kumar ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/374

Abstract: The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.