公开(公告)号：US10177035B2

公开(公告)日：2019-01-08

申请号：US15670809

申请日：2017-08-07

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Maeda

IPC: H01L21/8222 ,  H01L21/324 ,  H01L27/082 ,  H01L29/66 ,  H01L29/732 ,  H01L29/08

Abstract: It is prevented that when a predetermined number of semiconductor chips having transistors are manufactured from one semiconductor wafer, manufacturing cost of a semiconductor device is increased due to excess semiconductor chips manufactured from the semiconductor wafer. A first bipolar transistor including a first emitter region having a first area is formed in a first chip formation region in an exposure region that can be exposed by one exposure step, and a second bipolar transistor including a second emitter region having a second area different from the first area is formed in a second chip formation region in the exposure region.

公开(公告)号：US11217670B2

公开(公告)日：2022-01-04

申请号：US16722355

申请日：2019-12-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuji Takahashi ,  Masaki Watanabe ,  Masashi Sahara ,  Kentaro Yamada ,  Masaki Sakashita ,  Shinichi Maeda ,  Yoshiaki Yamada

IPC: H01L29/417 ,  H01L29/732 ,  H01L21/324 ,  H01L29/40 ,  H01L21/02 ,  H01L29/47

Abstract: A characteristic of a semiconductor device having a back electrode including an Au—Sb alloy is improved. The semiconductor device has a semiconductor substrate and the back electrode including the Au—Sb alloy layer. The back electrode is formed on the semiconductor substrate. The Sb concentration in the Au—Sb alloy layer is equal to or greater than 15 wt %, and equal to or less than 37 wt %. The thickness of the Au—Sb alloy layer is equal to or larger than 20 nm, and equal to or less than 45 nm.

公开(公告)号：US09728460B2

公开(公告)日：2017-08-08

申请号：US15278332

申请日：2016-09-28

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Maeda

IPC: H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L21/324

CPC classification number: H01L21/8222 ,  H01L21/324 ,  H01L27/082 ,  H01L29/0813 ,  H01L29/66303 ,  H01L29/732

Abstract: It is prevented that when a predetermined number of semiconductor chips having transistors are manufactured from one semiconductor wafer, manufacturing cost of a semiconductor device is increased due to excess semiconductor chips manufactured from the semiconductor wafer. A first bipolar transistor including a first emitter region having a first area is formed in a first chip formation region in an exposure region that can be exposed by one exposure step, and a second bipolar transistor including a second emitter region having a second area different from the first area is formed in a second chip formation region in the exposure region.