公开(公告)号：US10586777B2

公开(公告)日：2020-03-10

申请号：US15844223

申请日：2017-12-15

Applicant: Renesas Electronics Corporation

Inventor： Kentaro Yamada ,  Shigeki Tomaru ,  Taketoshi Fukushima

IPC: H01L23/00 ,  H01L23/528

Abstract: To improve the reliability of a semiconductor device.The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view.

公开(公告)号：US11217670B2

公开(公告)日：2022-01-04

申请号：US16722355

申请日：2019-12-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuji Takahashi ,  Masaki Watanabe ,  Masashi Sahara ,  Kentaro Yamada ,  Masaki Sakashita ,  Shinichi Maeda ,  Yoshiaki Yamada

IPC: H01L29/417 ,  H01L29/732 ,  H01L21/324 ,  H01L29/40 ,  H01L21/02 ,  H01L29/47

Abstract: A characteristic of a semiconductor device having a back electrode including an Au—Sb alloy is improved. The semiconductor device has a semiconductor substrate and the back electrode including the Au—Sb alloy layer. The back electrode is formed on the semiconductor substrate. The Sb concentration in the Au—Sb alloy layer is equal to or greater than 15 wt %, and equal to or less than 37 wt %. The thickness of the Au—Sb alloy layer is equal to or larger than 20 nm, and equal to or less than 45 nm.

公开(公告)号：US09349463B2

公开(公告)日：2016-05-24

申请号：US14679056

申请日：2015-04-06

Applicant: Renesas Electronics Corporation

Inventor： Shigeya Toyokawa ,  Michimoto Kaminaga ,  Kentaro Yamada

IPC: H01L27/108 ,  G11C16/12 ,  H01L27/115 ,  H01L29/788 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11558 ,  H01L29/7883

Abstract: To enhance the write speed of a nonvolatile memory. A charge injection/emission part of a nonvolatile memory cell includes an active region having an upper face, a side wall, and a shoulder part connecting the upper face and the side wall, a conductor film covering the upper face and the shoulder part of the active region, and a capacitance insulating film provided between the conductor film and the active region. Furthermore, the active region has a protrusion part constituted of a first concave part with respect to the upper face and a second concave part with respect to the side wall, in the shoulder part.

Abstract translation: 提高非易失性存储器的写入速度。 非易失性存储单元的电荷注入/发射部分包括具有上表面，侧壁和连接上表面和侧壁的肩部的有源区，覆盖上表面和侧壁的上表面和肩部的导体膜 有源区和设置在导体膜和有源区之间的电容绝缘膜。 此外，有源区具有在肩部中由相对于上表面的第一凹部和相对于侧壁的第二凹部构成的突出部。

公开(公告)号：US09935023B2

公开(公告)日：2018-04-03

申请号：US15630385

申请日：2017-06-22

Applicant: Renesas Electronics Corporation

Inventor： Toshikazu Hanawa ,  Kazuhide Fukaya ,  Kentaro Yamada

IPC: G01L21/30 ,  G01R31/00 ,  H01L21/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  G01N21/73 ,  G01N21/84 ,  G01N21/68 ,  H01J37/32

CPC classification number: H01L22/26 ,  G01N21/68 ,  G01N21/73 ,  G01N21/84 ,  G01N2021/8411 ,  G01N2021/8427 ,  G01N2201/1247 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329

Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.

公开(公告)号：US09711423B2

公开(公告)日：2017-07-18

申请号：US15205069

申请日：2016-07-08

Applicant: Renesas Electronics Corporation

Inventor： Toshikazu Hanawa ,  Kazuhide Fukaya ,  Kentaro Yamada

IPC: G01L21/30 ,  G01R31/00 ,  H01L21/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  G01N21/73 ,  G01N21/84

CPC classification number: H01L22/26 ,  G01N21/68 ,  G01N21/73 ,  G01N21/84 ,  G01N2021/8411 ,  G01N2021/8427 ,  G01N2201/1247 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329

Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.