公开(公告)号：US20230146858A1

公开(公告)日：2023-05-11

申请号：US17964276

申请日：2022-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MARUYAMA ,  Takuya HAGIWARA ,  Takuya MARUYAMA

IPC: H01L29/40 ,  H01L29/739 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L29/7397 ,  H01L21/31116

Abstract: A manufacturing method of a semiconductor device includes a step of preparing a semiconductor substrate having a first main surface and a second main surface, a step of forming a recess in the first main surface and embedding an insulating film in the recess, a step of forming a polysilicon film on the insulating film, a step of forming an interlayer insulating film on the first main surface so as to cover the insulating film and the polysilicon film, and a step of forming a first contact hole and a second contact hole. The semiconductor substrate has a first impurity diffusion region formed in the first main surface, and a second impurity diffusion region in contact with a portion of the first impurity diffusion region, the portion being closer to the second main surface.

公开(公告)号：US20240304680A1

公开(公告)日：2024-09-12

申请号：US18437947

申请日：2024-02-09

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MARUYAMA ,  Tomoki AYANO ,  Yuya ABIKO

IPC: H01L29/40 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L29/407 ,  H01L29/4236

Abstract: A field plate electrode is formed in an inside of a trench via a first insulating film. Another part of the field plate electrode is selectively removed such that part of the field plate electrode is left as a lead portion. After the first insulating film is recessed, a protective film is formed on the first insulating film. A gate insulating film is formed in the inside of the trench, and a second insulating film is formed so as to cover the field plate electrode. A conductive film is formed on the gate insulating, second insulating film and protective films. A gate electrode is formed on the field plate electrode by removing the conductive film located in an outside of the trench. At this time, the conductive film formed on each of the protective film and the second insulating film, which are in contact with the lead portion, is removed.

公开(公告)号：US20240164112A1

公开(公告)日：2024-05-16

申请号：US18054981

申请日：2022-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo OGURA ,  Takahiro MARUYAMA

IPC: H01L27/11592 ,  H01L27/1159

CPC classification number: H01L27/11592 ,  H01L27/1159

Abstract: This is a manufacturing method of a semiconductor device having a first region, a second region, and a third region. A second gate dielectric film is formed on a semiconductor substrate in the second region. A thin first gate dielectric film is formed on the semiconductor substrate in the first region. A protective film is formed on the first gate dielectric film and on the second gate dielectric film. A thin paraelectric film is formed on the semiconductor substrate in the third region. An amorphous film formed of a material including a metal oxide and a first element is formed on the protective film and on the paraelectric film. A metal film is formed on the amorphous film. By performing a heat treatment, the amorphous film is crystallized to form a ferroelectric film.

公开(公告)号：US20190206744A1

公开(公告)日：2019-07-04

申请号：US16192435

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MARUYAMA ,  Yoshiki YAMAMOTO ,  Toshiya SAITOH

IPC: H01L21/84 ,  H01L21/311 ,  H01L21/265 ,  H01L21/02 ,  H01L27/12

Abstract: A substrate including an insulating layer, a semiconductor layer, and an insulating film stacked on a semiconductor substrate and having a trench filled with an element isolation portion is provided. After removal of the insulating film from a bulk region by a first dry etching, the semiconductor layer is removed from the bulk region by a second dry etching. Then, the insulating film in an SOI region and the insulating layer in the bulk region are removed. A gas containing a fluorocarbon gas is used for first dry etching. The etching thickness of the element isolation portion by a first dry etching is at least equal to the sum of the thicknesses of the insulating film just before starting the first dry etching and the semiconductor layer just before starting the first dry etching. After first dry etching and before second dry etching, oxygen plasma treatment is performed.

公开(公告)号：US20160133507A1

公开(公告)日：2016-05-12

申请号：US14988013

申请日：2016-01-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsunori MURATA ,  Takahiro MARUYAMA

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/764

Abstract: An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.

公开(公告)号：US20160086961A1

公开(公告)日：2016-03-24

申请号：US14860700

申请日：2015-09-21

Applicant: Renesas Electronics Corporation

Inventor： Fukuo OWADA ,  Masaaki SHINOHARA ,  Takahiro MARUYAMA

IPC: H01L27/115

CPC classification number: H01L27/11546 ,  H01L27/11529

Abstract: An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film.

Abstract translation: 在半导体器件的性能方面实现了改进。 在位于存储器形成区域中的具有内部电荷存储部分的半导体衬底的主表面上形成的第一绝缘膜上，以及形成在位于主电路形成区域中的半导体衬底的主表面上的第二绝缘膜之上， 形成导电膜。 然后，在存储器形成区域中，对导电膜和第一绝缘膜进行构图以形成第一栅电极和第一栅极绝缘膜，同时在主电路形成区域中留下导电膜和第二绝缘膜。 然后，在主电路形成区域中，对导电膜和第二绝缘膜进行构图以形成第二栅极电极和第二栅极绝缘膜。

公开(公告)号：US20220149206A1

公开(公告)日：2022-05-12

申请号：US17521041

申请日：2021-11-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MARUYAMA

IPC: H01L29/78 ,  H01L27/1159 ,  H01L29/66

Abstract: A semiconductor device includes a ferroelectric memory having a ferroelectric film between a gate electrode and a semiconductor substrate. The ferroelectric film and a metal film are not formed just above an element isolation region formed in a trench in an upper surface of the semiconductor substrate, but are formed on the semiconductor substrate in the active region defined by the element isolation region to prevent a state in which a polarization state in the ferroelectric film of the active region and a polarization state in the ferroelectric film on the element isolation region differ from each other.

公开(公告)号：US20170092718A1

公开(公告)日：2017-03-30

申请号：US15374263

申请日：2016-12-09

Applicant: Renesas Electronics Corporation

Inventor： Tatsunori MURATA ,  Takahiro MARUYAMA

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/764

Abstract: An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.

公开(公告)号：US20250169137A1

公开(公告)日：2025-05-22

申请号：US18515087

申请日：2023-11-20

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MARUYAMA ,  Toshiya SAITO ,  Takuya MARUYAMA

IPC: H01L29/40

Abstract: A first conductive pattern is formed on a semiconductor substrate and formed from a first conductive film. A second conductive film having a first portion on the semiconductor substrate, a second portion on an upper surface of the first conductive pattern, and a third portion connecting the first portion and the second portion so as to cover a side surface of the first conductive pattern, is formed. The upper surface of the third portion is higher than the upper surface of the first portion. The second portion is patterned. The second portion and a part of the third portion are selectively removed. By patterning the first conductive pattern and the second conductive film, a first gate electrode is formed from a part of the first conductive pattern, and a second gate electrode is formed from a part of the first portion.

公开(公告)号：US20230420556A1

公开(公告)日：2023-12-28

申请号：US18179731

申请日：2023-03-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuya ABIKO ,  Takahiro MARUYAMA

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/401

Abstract: An improved power MOSFET of a split gate structure including a gate electrode and a field plate electrode in a trench is disclosed. The improved power MOSFET includes a field plate electrode FP formed at a lower portion of a trench TR and a gate electrode GE formed an upper portion of the trench TR. The field plate electrode FP further includes a contact portion FPa which is formed at the upper portion of the trench TR to provide a source potential. The gate electrode GE further includes a connecting portion GEa at the both sides of the contact portion FPa in the trench TR. The connecting portion GEa electrically connects between one portion of the gate electrode GE at a region 2A side and the other portion of the gate electrode GE at a region 2A′ side.