公开(公告)号：US20110198612A1

公开(公告)日：2011-08-18

申请号：US13012123

申请日：2011-01-24

Applicant: Rajesh Kumar MALHAN

Inventor： Rajesh Kumar MALHAN

IPC: H01L29/24 ,  H01L21/761

CPC classification number: H01L29/808 ,  H01L21/7602 ,  H01L21/8213 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/66068

Abstract: A SiC semiconductor device includes: a SiC substrate made of intrinsic SiC having semi-insulating property; first and second conductive type SiC layers disposed in the substrate; an insulation separation layer made of intrinsic SiC for isolating the first conductive type SiC layer from the second conductive type SiC layer; first and second conductive type channel JFETs disposed in the first and second conductive type SiC layers, respectively. The first and second conductive type channel JFETs provide a complementary junction field effect transistor. Since an electric element is formed on a flat surface, a manufacturing method is simplified. Further, noise propagation at high frequency and current leakage at high temperature are restricted.

Abstract translation: SiC半导体器件包括：由具有半绝缘性的本征SiC制成的SiC衬底; 设置在基板中的第一和第二导电型SiC层; 由本征SiC制成的绝缘分离层，用于将第一导电型SiC层与第二导电型SiC层隔离; 分别设置在第一和第二导电型SiC层中的第一和第二导电型沟道JFET。 第一和第二导电型沟道JFET提供互补结型场效应晶体管。 由于电气元件形成在平坦表面上，所以制造方法简单。 此外，高频下的噪声传播和高温下的电流泄漏受到限制。

公开(公告)号：US20120080728A1

公开(公告)日：2012-04-05

申请号：US13248173

申请日：2011-09-29

Applicant: Rajesh Kumar MALHAN

Inventor： Rajesh Kumar MALHAN

IPC: H01L29/812 ,  H01L21/337

CPC classification number: H01L29/8083 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/872

Abstract: A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.

Abstract translation: 公开了一种具有JFET的半导体器件。 半导体器件包括形成在沟槽中的沟槽和接触嵌入层。 栅极线连接到触点嵌入层，使得栅极线经由接触嵌入层连接到嵌入式栅极层。 在这种结构中，可以减小嵌入式栅极层与栅极线之间的接触结构。

公开(公告)号：US20110133211A1

公开(公告)日：2011-06-09

申请号：US12956152

申请日：2010-11-30

Applicant: Rajesh Kumar MALHAN ,  Naohiro Sugiyama ,  Yuuichi Takeuchi

Inventor： Rajesh Kumar MALHAN ,  Naohiro Sugiyama ,  Yuuichi Takeuchi

IPC: H01L29/161 ,  H01L29/812 ,  H01L29/78 ,  H01L29/80 ,  H01L21/337 ,  H01L21/338 ,  H01L21/336

CPC classification number: H01L29/808 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/8128

Abstract: A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.

Abstract translation: 具有JFET，MESFET或MOSFET的宽带隙半导体器件主要包括半导体衬底，第一导电类型半导体层和第一导电型沟道层。 半导体层形成在基板的主表面上。 在半导体层中以半导体层被分成源极区和漏极区的方式形成凹部。 凹部具有由基板的主表面和由半导体层限定的侧壁限定的底部。 沟道层的杂质浓度低于半导体层的杂质浓度。 沟槽层通过外延生长形成在凹部的底部和侧壁上。

公开(公告)号：US20110254177A1

公开(公告)日：2011-10-20

申请号：US13171788

申请日：2011-06-29

Applicant: Rajesh Kumar MALHAN ,  C Mark JOHNSON ,  Cyril BUTTAY ,  Jeremy RASHID ,  Florin UDREA

Inventor： Rajesh Kumar MALHAN ,  C Mark JOHNSON ,  Cyril BUTTAY ,  Jeremy RASHID ,  Florin UDREA

IPC: H01L23/48

CPC classification number: H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Abstract translation: 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。

公开(公告)号：US20110186861A1

公开(公告)日：2011-08-04

申请号：US13014037

申请日：2011-01-26

Applicant: Rajesh Kumar MALHAN ,  Masaaki KUZUHARA

Inventor： Rajesh Kumar MALHAN ,  Masaaki KUZUHARA

IPC: H01L29/12 ,  H01L29/812 ,  H01L21/338

CPC classification number: H01L29/12 ,  H01L29/812

Abstract: A semiconductor device having a JFET or a MESFET mainly includes a semiconductor substrate, a first conductivity type semiconductor channel layer on the substrate, a first conductivity type semiconductor layer on the channel layer, and an i-type sidewall layer on a sidewall of a recess that penetrates the semiconductor layer to divide the semiconductor layer into a source region and a drain region. The semiconductor layer has an impurity concentration greater than an impurity concentration of the channel layer. The semiconductor device further includes a second conductivity type gate region that is located on the channel layer in the recess and on the i-type sidewall layer. The gate region is spaced from the source region and the drain region by the i-type sidewall layer.

Abstract translation: 具有JFET或MESFET的半导体器件主要包括半导体衬底，衬底上的第一导电类型半导体沟道层，沟道层上的第一导电类型半导体层以及凹槽侧壁上的i型侧壁层 其穿透半导体层以将半导体层分成源极区和漏极区。 半导体层的杂质浓度大于沟道层的杂质浓度。 半导体器件还包括位于凹槽中和i型侧壁层上的沟道层上的第二导电型栅极区域。 栅极区域通过i型侧壁层与源极区域和漏极区域间隔开。

公开(公告)号：US20110002083A1

公开(公告)日：2011-01-06

申请号：US12830517

申请日：2010-07-06

Applicant: Rajesh Kumar MALHAN ,  Naohiro SUGIYAMA ,  Yuji NOGUCHI ,  Masaru MIYAYAMA

Inventor： Rajesh Kumar MALHAN ,  Naohiro SUGIYAMA ,  Yuji NOGUCHI ,  Masaru MIYAYAMA

IPC: H01G4/06 ,  C04B35/00 ,  C04B35/50

CPC classification number: H01G4/1227 ,  C04B35/4682 ,  C04B35/49 ,  C04B35/495 ,  C04B2235/3206 ,  C04B2235/3215 ,  C04B2235/3236 ,  C04B2235/3255 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/656 ,  C04B2235/6567 ,  C04B2235/662 ,  C04B2235/77 ,  C04B2235/81 ,  H01G4/0085 ,  H01G4/30

Abstract: A ceramic material has a perovskite structure and is represented by formula of (1−x)ABO3-xYZO3. In the formula, “x” is a real number that is greater than 0 and is less than 1 each of “A,” “B,” “Y,” and “Z” is one or more kinds selected from a plurality of metal ions M other than a Pb ion and alkali metal ions, “A” is bivalent, “B” is tetravalent, “Y” is trivalent or combination of trivalent metal ions, and “Z” is bivalent and/or trivalent metal ions, or a bivalent and/or pentavalent metal ions.

Abstract translation: 陶瓷材料具有钙钛矿结构并由（1-x）ABO 3-x YZO 3的式表示。 在该公式中，“x”是大于0并且小于“A”，“B”，“Y”“的1的实数，”Z“是从多个金属中选择的一种或多种 离子M除了Pb离子和碱金属离子之外，“A”为二价，“B”为四价，“Y”为三价金属离子或三价金属离子的组合，“Z”为二价和/或三价金属离子，或 二价和/或五价金属离子。