公开(公告)号：US20160260824A1

公开(公告)日：2016-09-08

申请号：US14986150

申请日：2015-12-31

申请人： Florin Udrea ,  Alice Pei-Shan Hsieh ,  Gianluca Camuso ,  Chiu Ng ,  Yi Tang ,  Rajeev Krishna Vytla

发明人： Florin Udrea ,  Alice Pei-Shan Hsieh ,  Gianluca Camuso ,  Chiu Ng ,  Yi Tang ,  Rajeev Krishna Vytla

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/7397 ,  H01L29/0634 ,  H01L29/41708 ,  H01L29/7394

摘要： There are disclosed herein various implementations of a bipolar semiconductor device having a charge-balanced inter-trench structure. Such a device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type. The device also includes first and second control trenches extending through an inversion region having the second conductivity type into the drift region, each of the first and second control trenches being bordered by a cathode diffusion having the first conductivity type. In addition, the device includes an inter-trench structure situated in the drift region between the first and second control trenches. The inter-trench structure includes one or more first conductivity regions having the first conductivity type and one or more second conductivity region having the second conductivity type, the one or more first conductivity regions and the one or more second conductivity regions configured to substantially charge-balance the inter-trench structure.

摘要翻译： 这里公开了具有电荷平衡的沟槽间结构的双极半导体器件的各种实施方式。 这种器件包括位于具有第二导电类型的阳极层上的具有第一导电类型的漂移区。 该器件还包括延伸穿过具有第二导电类型的反向区域到漂移区域中的第一和第二控制沟槽，第一和第二控制沟槽中的每一个都由具有第一导电类型的阴极扩散区界定。 此外，该器件包括位于第一和第二控制沟槽之间的漂移区域中的沟槽间结构。 沟槽间结构包括具有第一导电类型的一个或多个第一导电区域和具有第二导电类型的一个或多个第二导电区域，一个或多个第一导电区域和一个或多个第二导电区域， 平衡沟槽间结构。

公开(公告)号：US08816468B2

公开(公告)日：2014-08-26

申请号：US13222249

申请日：2011-08-31

申请人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

发明人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

IPC分类号： H01L29/872

CPC分类号： H01L29/66143 ,  H01L21/22 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

摘要翻译： 半导体整流器包括具有第一类导电性的半导体衬底。 形成在基板上的第一层具有第一类导电性，并且比衬底更轻掺杂。 在基板上形成具有第二导电类型的第二层，并且金属层设置在第二层上。 第二层被轻掺杂，使得在金属层和第二层之间形成肖特基接触。 第一电极形成在金属层的上方，第二电极形成在基板的背面。

公开(公告)号：US20110227152A1

公开(公告)日：2011-09-22

申请号：US12909033

申请日：2010-10-21

申请人： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

发明人： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

IPC分类号： H01L27/06

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.

摘要翻译： 功率晶体管的端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界延伸到半导体衬底的边缘的一定距离内。 掺杂区域具有设置在终端沟槽下方的衬底中的第二类型的导电体。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与边界间隔开的部分MOS栅极的下方延伸到终端沟槽的远侧侧壁。 端接结构氧化物层形成在终端沟槽上并且覆盖MOS栅极的一部分并朝向衬底的边缘延伸。 第一导电层形成在半导体衬底的背面上。 第二导电层形成在有源区顶部，MOS栅极的暴露部分的顶部，并延伸以覆盖端接结构氧化物层的至少一部分。

公开(公告)号：US07999369B2

公开(公告)日：2011-08-16

申请号：US11511516

申请日：2006-08-29

申请人： Rajesh Kumar Malhan ,  C. Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

发明人： Rajesh Kumar Malhan ,  C. Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

IPC分类号： H01L23/48

CPC分类号： H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

摘要翻译： 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。

公开(公告)号：US20110174799A1

公开(公告)日：2011-07-21

申请号：US12691104

申请日：2010-01-21

申请人： Syed Zeeshan ALI ,  Florin Udrea ,  Julian William Gardner

发明人： Syed Zeeshan ALI ,  Florin Udrea ,  Julian William Gardner

IPC分类号： H05B3/68 ,  H01L21/3065 ,  H01L21/306

CPC分类号： H05B3/267 ,  Y10T29/49083

摘要： A micro-hotplate is provided in the form of a device comprising a sensor and one or more resistive heaters within the micro-hotplate arranged to heat the sensor. Furthermore a controller is provided for applying a bidirectional drive current to at least one of the heaters to reduce electromigration. The controller also serves to drive the heater at a substantially constant temperature. Such an arrangement is advantageous over an arrangement in which a unidirectional DC drive current is applied to the heater. This is because the unidirectional drive current causes electromigration which results in an increase in resistance over time. This is undesirable because it can lead to failure of the micro-hotplate. In contrast, the application of the bidirectional current reduces electromigration and as a result there is insignificant change in the resistance of the heater over time and under high temperature. This in turn improves the reliability of the micro-hotplate and therefore helps to improve the lifetime of the sensor

摘要翻译： 提供微电子装置的形式包括传感器和微电热板内的一个或多个电阻加热器，其布置成加热传感器。 此外，提供了一种控制器，用于向至少一个加热器施加双向驱动电流以减少电迁移。 控制器还用于以基本恒定的温度驱动加热器。 这种布置对于将单向DC驱动电流施加到加热器的布置是有利的。 这是因为单向驱动电流导致电迁移，导致电阻随时间的增加。 这是不希望的，因为它可能导致微电热板的故障。 相比之下，双向电流的应用减少了电迁移，结果是随着时间的推移和高温下电阻的电阻变化不大。 这又提高了微型电热板的可靠性，因此有助于提高传感器的使用寿命

公开(公告)号：US07821013B2

公开(公告)日：2010-10-26

申请号：US11501777

申请日：2006-08-10

申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC分类号： H01L29/12 ,  H01L29/41

CPC分类号： H01L29/8083 ,  H01L29/1608

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

公开(公告)号：US07679160B2

公开(公告)日：2010-03-16

申请号：US11216197

申请日：2005-09-01

申请人： Florin Udrea ,  Gehan Anil Joseph Amaratunga

发明人： Florin Udrea ,  Gehan Anil Joseph Amaratunga

IPC分类号： H01L29/93

CPC分类号： H01L29/86 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0634 ,  H01L29/66325 ,  H01L29/7317 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/78603 ,  H01L29/868 ,  H02M7/003

摘要： A high voltage/power semiconductor device has at least one active region having a plurality of high voltage junctions electrically connected in parallel. At least part of each of the high voltage junctions is located in or on a respective membrane such that the active region is provided at least in part over plural membranes. There are non-membrane regions between the membranes. The device has a low voltage terminal and a high voltage terminal. At least a portion of the low voltage terminal and at least a portion of the high voltage terminal are connected directly or indirectly to a respective one of the high voltage junctions. At least those portions of the high voltage terminal that are in direct or indirect contact with one of the high voltage junctions are located on or in a respective one of the plural membranes.

摘要翻译： 高电压/功率半导体器件具有至少一个有源区，其具有并联电连接的多个高电压结。 每个高电压接头的至少一部分位于相应的膜中或上，使得有源区至少部分地设置在多个膜上。 膜之间有非膜区。 该器件具有低电压端子和高压端子。 低电压端子的至少一部分和高电压端子的至少一部分直接或间接地连接到相应的一个高压接点。 至少与高压接点中的一个直接或间接接触的高压端子的那些部分位于多个膜中的相应的一个上或其中。

公开(公告)号：US20090160015A1

公开(公告)日：2009-06-25

申请号：US11961410

申请日：2007-12-20

申请人： Florin UDREA ,  Gehan Anil Joseph Amaratunga ,  Tanya Trajkovic ,  Vasantha Pathirana

发明人： Florin UDREA ,  Gehan Anil Joseph Amaratunga ,  Tanya Trajkovic ,  Vasantha Pathirana

IPC分类号： H01L29/06 ,  H01L21/306

CPC分类号： H01L29/0657 ,  H01L21/8249 ,  H01L22/26 ,  H01L29/063 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/7393 ,  H01L29/7816

摘要： In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.

摘要翻译： 在功率半导体器件和形成功率半导体器件的方法中，将半导体衬底的薄层留在半导体器件的漂移区域的下方。 功率半导体器件具有包括漂移区的有源区，并且具有形成在设置在半导体衬底上的层中的顶表面和底表面。 在有源区下面的半导体衬底的一部分被去除以在漂移区下方留下半导体衬底的薄层。 电端子直接或间接提供到有源区的顶表面，以允许电压横向跨越漂移区域施加。

公开(公告)号：US07531993B2

公开(公告)日：2009-05-12

申请号：US11847234

申请日：2007-08-29

申请人： Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

发明人： Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

IPC分类号： G05F3/16 ,  H03K3/35

CPC分类号： H03K17/567 ,  H01L29/0638 ,  H01L29/7393 ,  H03K17/08142 ,  H03K17/6871 ,  H03K2017/6878

摘要： A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.

摘要翻译： 半桥电路具有具有至少一个控制栅极的第一开关和具有至少两个控制栅极的第二开关。 第一驱动器具有连接到第一开关的控制栅极的输出端。 第二驱动器具有连接到第二开关的第一控制栅极的输出。 第一驱动器的输出通过电路装置连接到第二开关的第二控制栅极，使得当第一驱动器被操作以向第一开关的控制栅极施加高正正电压时，施加正电压 并且使得当第一驱动器被操作以向第一开关的控制栅极施加低，零或小电压时，负电压被施加到第二开关的第二控制栅极的第二控制栅极 开关。

公开(公告)号：US07485509B2

公开(公告)日：2009-02-03

申请号：US11594896

申请日：2006-11-09

申请人： Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

发明人： Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66068 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/1608 ,  H01L29/808 ,  H01L29/8083

摘要： A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the source of the first field effect transistor. The gate of the second field effect transistor connects to the gate of the first field effect transistor.

摘要翻译： 半导体器件包括：第一场效应晶体管，其包括源极和栅极，并设置在碳化硅衬底中; 以及包括漏极和栅极并设置在所述衬底中的第二场效应晶体管。 第二场效应晶体管的漏极连接到第一场效应晶体管的源极。 第二场效应晶体管的栅极连接到第一场效应晶体管的栅极。