公开(公告)号：US06352871B1

公开(公告)日：2002-03-05

申请号：US09409089

申请日：1999-09-30

申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Glen Gilfeather

发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Glen Gilfeather

IPC分类号： H01L2166

CPC分类号： G01R31/312 ,  G01R31/2884 ,  G01R31/303

摘要： The ability to excite virtually any portion of semiconductor device is enhanced via a grid formed for exciting circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for exciting various target circuitry within the device by exciting the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

摘要翻译： 实际上激发半导体器件的任何部分的能力通过为半导体器件中的激励电路形成的电网来增强。 根据本发明的一个示例性实施例，在半导体器件中形成有延伸超过目标电路的具有多个窄探针点的格栅。 电网被访问并用于通过激励对应于期望访问的目标电路的部分的电网部分来激发装置内的各种目标电路。

公开(公告)号：US06455334B1

公开(公告)日：2002-09-24

申请号：US09409982

申请日：1999-09-30

申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Glen Gilfeather

发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Glen Gilfeather

IPC分类号： H01L2166

CPC分类号： G01R31/2884 ,  Y10S438/977 ,  Y10S977/854

摘要： The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

摘要翻译： 通过形成用于分析半导体器件中的电路的栅格来增强对几乎任何部分的半导体器件的监视能力。 根据本发明的一个示例性实施例，在半导体器件中形成有延伸超过目标电路的具有多个窄探针点的格栅。 电网被访问并用于通过访问对应于期望接入的目标电路的部分的网格部分来监视设备内的各种目标电路。

公开(公告)号：US06469529B1

公开(公告)日：2002-10-22

申请号：US09580716

申请日：2000-05-30

申请人： Michael R. Bruce ,  Rama R. Goruganthu ,  Glen Gilfeather

发明人： Michael R. Bruce ,  Rama R. Goruganthu ,  Glen Gilfeather

IPC分类号： G01R31302

CPC分类号： G01R31/311

摘要： Integrated circuit devices are analyzed using an integrated system adapted to obtain time-resolved information from the back side of a silicon based semiconductor chip using hot carrier emissions. According to an example embodiment of the present invention, a system is adapted to analyze a semiconductor device under test (DUT) using a plurality of sensors mounted to a microscope having an objective lens. The plurality of sensors include a global acquisition sensor, a single-point acquisition sensor, and a navigation sensor. The integrated system is adapted to use the plurality of sensors individually and simultaneously. The integrated system improves the analysis of the DUT for reasons including that it makes possible the performance of more than one type of analysis simultaneously using a single test arrangement.

摘要翻译： 使用集成系统分析集成电路器件，该系统适于使用热载流子发射从硅基半导体芯片的背面获得时间分辨信息。 根据本发明的示例性实施例，系统适用于使用安装在具有物镜的显微镜上的多个传感器来分析被测半导体器件（DUT）。 多个传感器包括全局采集传感器，单点采集传感器和导航传感器。 集成系统适于单独和同时使用多个传感器。 集成系统改进了DUT的分析原因，包括使用单个测试装置可以同时执行多种类型的分析。

公开(公告)号：US06566888B1

公开(公告)日：2003-05-20

申请号：US09833250

申请日：2001-04-11

申请人： Michael R. Bruce ,  Glen Gilfeather ,  Rama R. Goruganthu

发明人： Michael R. Bruce ,  Glen Gilfeather ,  Rama R. Goruganthu

IPC分类号： G01R3108

CPC分类号： H01L22/22 ,  H01L21/76894

摘要： The present invention is directed to the repair of resistive circuitry in an integrated circuit die having a multitude of circuit paths. According to an example embodiment of the present invention, a semiconductor die having a resistive electrical connection is analyzed. The location of a circuit portion in the die having a resistive electrical connection is identified. Using the identified location, the resistive circuit portion is annealed and the resistivity of that circuit portion is reduced. The reduced resistivity improves the ability of the die to operate at high speeds, and makes possible the repair and subsequent use of the die in various applications.

摘要翻译： 本发明涉及具有多个电路路径的集成电路管芯中的电阻电路的修复。 根据本发明的示例性实施例，分析具有电阻电连接的半导体管芯。 识别具有电阻电连接的管芯中的电路部分的位置。 使用识别的位置，对电阻电路部分进行退火，并减小该电路部分的电阻率。 降低的电阻率提高了模具在高速下运行的能力，并且使得可以在各种应用中修复和随后使用模具。

公开(公告)号：US06372627B1

公开(公告)日：2002-04-16

申请号：US09383790

申请日：1999-08-26

申请人： Rosalinda M. Ring ,  Susan Li ,  Glen Gilfeather

发明人： Rosalinda M. Ring ,  Susan Li ,  Glen Gilfeather

IPC分类号： H01L217463

CPC分类号： G01R31/2884 ,  G01R31/2851 ,  G01R31/2898 ,  G01R31/311

摘要： According to one aspect of the disclosure and a particular example application directed to a flip-chip packaged die, a method for acquiring a signal from a target node in the circuit side includes removing substrate via the back side of the die to form an access area over the target node. A material is deposited in the access area over the target node in such a way to form simultaneously a conductive core and an immediately adjacent insulator. The conductive core is then used to couple a test signal between the target node and the conductive core. Other aspects of the disclosure include using a focused ion-beam system to provide varying concentrations of Gallium in forming simultaneously the conductive core and the immediately adjacent insulator. These aspects significantly lessen integrated circuit analysis and testing procedures.

摘要翻译： 根据本公开的一个方面和针对倒装芯片封装芯片的特定示例应用，从电路侧的目标节点获取信号的方法包括经由裸片的背面去除衬底以形成接近区域 在目标节点上。 材料沉积在目标节点上的进入区域中，以同时形成导电芯和紧邻的绝缘体。 然后使用导电芯将目标节点和导电芯之间的测试信号耦合。 本公开的其他方面包括使用聚焦离子束系统来在形成导电芯和紧邻的绝缘体的同时提供不同浓度的镓。 这些方面显着降低了集成电路分析和测试程序。

公开(公告)号：US6069366A

公开(公告)日：2000-05-30

申请号：US50531

申请日：1998-03-30

申请人： Rama R. Goruganthu ,  Victoria J. Bruce ,  Glen Gilfeather

发明人： Rama R. Goruganthu ,  Victoria J. Bruce ,  Glen Gilfeather

IPC分类号： G01R31/28 ,  G01R31/311 ,  G01N21/86

CPC分类号： G01R31/2898 ,  G01R31/2851 ,  G01R31/311

摘要： A system for determining the endpoint associated with removing silicon from the backside of a flip chip type die includes a tool for removing silicon and a light source for directing light to the backside of the die. An electrical measuring apparatus, such as a voltmeter, ammeter or oscilloscope, is attached across the output pins of a package to which the die is attached. The light or ions directed toward the backside of the die induce a current in the devices formed in the semiconductor. The value of the current or voltage output depends on the thickness of material between the endpoint on the backside of the die and the devices in the epitaxial layer of the die. The induced signal can be monitored to determine the thickness. Silicon can be removed globally until the thickness is reasonable such that a local thinning tool can be used to remove silicon to get to the area of interest in a reasonable amount of time. The induced current can be monitored during local thinning. A viewing mechanism such as infrared microscopy can be used to locate the specific device or devices of interest in the epitaxial layer of the die. The viewing mechanism is also used to determine where localized thinning will occur.

摘要翻译： 用于确定与从倒装芯片型芯片的背面移除硅相关联的端点的系统包括用于去除硅的工具和用于将光引导到裸片的背面的光源。 诸如电压表，电流表或示波器的电气测量装置被安装在与芯片连接的封装的输出引脚上。 指向芯片背面的光或离子在半导体中形成的器件中引起电流。 电流或电压输出的值取决于管芯背面端点与管芯外延层器件之间的材料厚度。 可以监测感应信号以确定厚度。 可以全局去除硅，直到厚度合理，使得可以使用局部稀化工具在合理的时间量内去除硅以达到感兴趣的区域。 在局部变薄期间可以监测感应电流。 可以使用诸如红外显微镜的观察机构在模具的外延层中定位感兴趣的特定器件或器件。 观察机制也用于确定发生局部变薄的位置。

公开(公告)号：US06285036B1

公开(公告)日：2001-09-04

申请号：US09578195

申请日：2000-05-24

申请人： Rama R. Goruganthu ,  Victoria J. Bruce ,  Glen Gilfeather

发明人： Rama R. Goruganthu ,  Victoria J. Bruce ,  Glen Gilfeather

IPC分类号： G01N2186

CPC分类号： G01R31/2898 ,  G01R31/2851 ,  G01R31/311

摘要： A system for determining the endpoint associated with removing silicon from the backside of a flip chip type die includes a tool for removing silicon and a light source for directing light to the backside of the die. An electrical measuring apparatus, such as a voltmeter, ammeter or oscilloscope, is attached across the output pins of a package to which the die is attached. The light or ions directed toward the backside of the die induce a current in the devices formed in the semiconductor. The value of the current or voltage output depends on the thickness of material between the endpoint on the backside of the die and the devices in the epitaxial layer of the die. The induced signal can be monitored to determine the thickness. Silicon can be removed globally until the thickness is reasonable such that a local thinning tool can be used to remove silicon to get to the area of interest in a reasonable amount of time. The induced current can be monitored during local thinning. A viewing mechanism such as infrared microscopy can be used to locate the specific device or devices of interest in the epitaxial layer of the die. The viewing mechanism is also used to determine where localized thinning will occur.

摘要翻译： 用于确定与从倒装芯片型芯片的背面移除硅相关联的端点的系统包括用于去除硅的工具和用于将光引导到裸片的背面的光源。 诸如电压表，电流表或示波器的电气测量装置被安装在与芯片连接的封装的输出引脚上。 指向芯片背面的光或离子在半导体中形成的器件中引起电流。 电流或电压输出的值取决于管芯背面端点与管芯外延层器件之间的材料厚度。 可以监测感应信号以确定厚度。 可以全局去除硅，直到厚度合理，使得可以使用局部稀化工具在合理的时间量内去除硅以达到感兴趣的区域。 在局部变薄期间可以监测感应电流。 可以使用诸如红外显微镜的观察机构在模具的外延层中定位感兴趣的特定器件或器件。 观察机制也用于确定发生局部变薄的位置。

公开(公告)号：US07088852B1

公开(公告)日：2006-08-08

申请号：US09833247

申请日：2001-04-11

申请人： Michael R. Bruce ,  Victoria J Bruce ,  Glen Gilfeather

发明人： Michael R. Bruce ,  Victoria J Bruce ,  Glen Gilfeather

IPC分类号： G06K9/00

CPC分类号： G01N23/2251

摘要： Defect analysis of a semiconductor die is enhanced in a manner that makes possible the viewing of spatial manifestations of the defect from virtually any angle. According to an example embodiment of the present invention, substrate is removed from a semiconductor die while simultaneously obtaining images of the portions of the die from which substrate is being removed. The images are taken at various points in the substrate removal process, recorded and combined together to form a three-dimensional image of selected portions of the die. The image is then used to view the selected portions, and the nature of one or more defects therein are analyzed.

摘要翻译： 增强半导体裸片的缺陷分析，使得可以从几乎任何角度观察缺陷的空间表现。 根据本发明的示例性实施例，从半导体管芯移除衬底，同时获得正在去除衬底的管芯的部分的图像。 在基板去除过程中的各个点拍摄图像，记录并组合在一起，以形成模具的所选部分的三维图像。 然后使用该图像来查看所选择的部分，并且分析其中的一个或多个缺陷的性质。

公开(公告)号：US06833718B1

公开(公告)日：2004-12-21

申请号：US10324328

申请日：2002-12-20

申请人： David Bethke ,  Michael R. Bruce ,  Shawn M. McBride ,  Greg Dabney ,  Glen Gilfeather ,  Rama Goruganthu

发明人： David Bethke ,  Michael R. Bruce ,  Shawn M. McBride ,  Greg Dabney ,  Glen Gilfeather ,  Rama Goruganthu

IPC分类号： G01R31302

CPC分类号： G01R31/311

摘要： Various apparatus and methods for enhancing hot-electron luminescence in an integrated circuit are provided. In one aspect, an apparatus is provided that includes a first circuit device coupled to a first voltage source that is operable to bias the first circuit device to a first voltage, and a second circuit device that has a first input coupled to the first voltage source and a junction defining a first side and a second side. One of the first and second sides is coupled to a second voltage source that is independent of the first voltage source and capable of selectively biasing the one of the first and second sides at a second voltage higher than the first voltage. The second device is operable to emit a hot-electron induced photon upon entry into saturation.

摘要翻译： 提供了用于增强集成电路中的热电子发光的各种装置和方法。 一方面，提供了一种装置，其包括耦合到第一电压源的第一电路装置，其可操作以将第一电路装置偏置到第一电压，以及第二电路装置，其具有耦合到第一电压源 以及限定第一侧和第二侧的接合部。 第一和第二侧中的一个耦合到独立于第一电压源的第二电压源，并且能够以比第一电压高的第二电压选择性地偏置第一和第二侧中的一个。 第二装置可操作以在进入饱和时发射热电子诱导光子。

公开(公告)号：US06171944B2

公开(公告)日：2001-01-09

申请号：US09074627

申请日：1998-05-07

申请人： Xia Li ,  Glen Gilfeather

发明人： Xia Li ,  Glen Gilfeather

IPC分类号： H01L214763

CPC分类号： H01L21/76892 ,  H01L21/31155 ,  H01L21/76805

摘要： A method for bringing up lower level metal nodes of multi-layered IC devices (200) includes a step of boring a passage (210) down through the obstructing or non-target metal layers (220) exposing these layers, through the Inter Layer Dielectric layers (230), stopping at the target metal layer (240), and a step of depositing Gallium implanted insulator (250, 260) forming a node structure (280) with a conductive core (250) and an insulative sheath (260). The conductive core (250) brings up the target metal node or layer (240) and the insulative sheath (260) isolates the exposed non-target metal nodes or layers (220) from the target metal node (240) and the conductive core (250).

摘要翻译： 一种用于提升多层IC器件（200）的下层金属节点的方法包括将通道（210）向下穿过暴露这些层的阻挡或非目标金属层（220）穿过层间介质 在所述目标金属层（240）处停止的层（230），以及形成具有导电芯（250）和绝缘护套（260）的形成节点结构（280）的镓注入绝缘体（250,260）的步骤。 导电芯（250）引出目标金属节点或层（240），并且绝缘护套（260）将暴露的非目标金属节点或层（220）与目标金属节点（240）和导电芯 250）。