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公开(公告)号：US20210203530A1
公开(公告)日：2021-07-01
申请号：US17247932
申请日：2020-12-30
Applicant: Rambus Inc.
Inventor： Kamran Farzan , Dongyun Lee
Abstract: A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.
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公开(公告)号：US20250036304A1
公开(公告)日：2025-01-30
申请号：US18786883
申请日：2024-07-29
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Dongyun Lee
IPC: G06F3/06
Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.
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公开(公告)号：US12067294B2
公开(公告)日：2024-08-20
申请号：US17833657
申请日：2022-06-06
Applicant: Rambus Inc.
Inventor： Dongyun Lee
IPC: G11C7/10 , G06F3/06 , G11C11/4093
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0673 , G11C7/1093 , G11C11/4093
Abstract: Technologies for converting serial data stream to a parallel data and strobe scheme with data strobe preamble information in the serial data stream are described. A device includes an interface circuit that receives a serial data stream and converts the serial data stream to parallel data and a data strobe (DQS) signal associated with the parallel data using N-bit header fields inserted into the serial data stream. The N-bit header fields specify DQS preamble information for the parallel data.
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公开(公告)号：US11750426B2
公开(公告)日：2023-09-05
申请号：US17864100
申请日：2022-07-13
Applicant: Rambus Inc.
Inventor： Kamran Farzan , Dongyun Lee
Abstract: A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.
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公开(公告)号：US20230087576A1
公开(公告)日：2023-03-23
申请号：US17940956
申请日：2022-09-08
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Dongyun Lee
IPC: G06F3/06
Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.
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Patent Agency Ranking
公开(公告)号：US10887137B2
公开(公告)日：2021-01-05
申请号：US16817171
申请日：2020-03-12
Applicant: Rambus Inc.
Inventor： Kamran Farzan , Dongyun Lee
Abstract: A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.
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公开(公告)号：US20200295978A1
公开(公告)日：2020-09-17
申请号：US16817171
申请日：2020-03-12
Applicant: Rambus Inc.
Inventor： Kamran Farzan , Dongyun Lee
Abstract: A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.
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公开(公告)号：US12073111B2
公开(公告)日：2024-08-27
申请号：US17940956
申请日：2022-09-08
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Dongyun Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673
Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.
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公开(公告)号：US20230176953A1
公开(公告)日：2023-06-08
申请号：US18059900
申请日：2022-11-29
Applicant: Rambus Inc.
Inventor： Joohee Kim , Dongyun Lee
IPC: G06F11/20 , H01L23/00 , H01L25/065 , G11C29/00
CPC classification number: G06F11/2028 , H01L24/32 , H01L24/16 , H01L25/0657 , G11C29/816 , H01L2225/06513 , H01L2225/06517 , H01L2224/32145 , H01L2924/15311
Abstract: Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.
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公开(公告)号：US11646284B2
公开(公告)日：2023-05-09
申请号：US17493264
申请日：2021-10-04
Applicant: Rambus Inc.
Inventor： Dongyun Lee , Ming Li
IPC: G11C29/12 , H01L23/00 , H01L25/065 , H01L21/66
CPC classification number: H01L24/08 , G11C29/1201 , H01L22/34 , H01L25/0657 , H01L2224/08145 , H01L2924/1436 , H01L2924/37001
Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die having a first bonding surface that is formed with a first set of contacts patterned with a first connection pitch. A second semiconductor die has a second bonding surface that is formed with a second set of contacts patterned with a second connection pitch. The second set of contacts are further patterned with a paired offset. The second semiconductor die is bonded to the first semiconductor die such that the first set of contacts is disposed in opposed electrical engagement with at least a portion of the second set of contacts.
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