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公开(公告)号:US06815757B2
公开(公告)日:2004-11-09
申请号:US10349066
申请日:2003-01-22
IPC分类号: H01L29788
CPC分类号: H01L29/66825 , H01L27/115 , H01L29/0692 , H01L29/7883
摘要: Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).
摘要翻译: 公开了用于制造用于负偏压衬底(12)的EEPROM存储器单元(10)的器件和相关方法。 本发明可以使用标准半导体处理技术来实施。 公开了用作浮动栅晶体管的器件和方法,用作EEPROM单元(10),其包括形成在P型衬底(12)上的DNwell(14),用于将EEPROM单元(10)与下面的P型衬底 (12)。
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公开(公告)号:US07039888B2
公开(公告)日:2006-05-02
申请号:US10728068
申请日:2003-12-04
CPC分类号: H01L28/20 , G01R31/2846 , G01R31/2884 , G01R31/2891 , H01L27/016
摘要: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.
摘要翻译: 提出了一种方法,其中薄膜电阻器被建模以考虑自热。 该方法包括制造薄膜电阻器并表征薄膜电阻器的热阻,其中热电阻在操作期间占其自身加热。 然后将热阻用于模拟使用薄膜电阻器的集成电路的模型中。
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公开(公告)号:US20050124079A1
公开(公告)日:2005-06-09
申请号:US10728068
申请日:2003-12-04
CPC分类号: H01L28/20 , G01R31/2846 , G01R31/2884 , G01R31/2891 , H01L27/016
摘要: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.
摘要翻译: 提出了一种方法,其中薄膜电阻器被建模以考虑自热。 该方法包括制造薄膜电阻器并表征薄膜电阻器的热阻,其中热电阻在操作期间占其自身加热。 然后将热阻用于模拟使用薄膜电阻器的集成电路的模型中。
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公开(公告)号:US06747308B2
公开(公告)日:2004-06-08
申请号:US10334319
申请日:2002-12-30
申请人: Jozef C. Mitros , Lily Springer , Roland Bucksch
发明人: Jozef C. Mitros , Lily Springer , Roland Bucksch
IPC分类号: H01L29788
CPC分类号: H01L29/7885 , G11C2216/10 , H01L27/115 , H01L29/42324
摘要: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.
摘要翻译: EEPROM(100)包括源区(122),漏区(120); 和多晶硅层(110)。 多晶硅层(110)包括浮动栅极,其包括可操作地耦合源极区域(122)和漏极区域(120)的至少一个多晶硅指状物(112A-112E)和包括至少一个多晶硅指状物(112A- 112E)电容耦合到浮动栅极。 与现有技术的EEPROM相比,EEPROM(100)具有大大减小的面积,因为消除了n阱区域。
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