公开(公告)号：US06815757B2

公开(公告)日：2004-11-09

申请号：US10349066

申请日：2003-01-22

申请人： Reed W. Adams ,  William E. Grose ,  Sameer Pendharkar ,  Roland Bucksch

发明人： Reed W. Adams ,  William E. Grose ,  Sameer Pendharkar ,  Roland Bucksch

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/0692 ,  H01L29/7883

摘要： Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).

摘要翻译： 公开了用于制造用于负偏压衬底（12）的EEPROM存储器单元（10）的器件和相关方法。 本发明可以使用标准半导体处理技术来实施。 公开了用作浮动栅晶体管的器件和方法，用作EEPROM单元（10），其包括形成在P型衬底（12）上的DNwell（14），用于将EEPROM单元（10）与下面的P型衬底 （12）。

公开(公告)号：US09385196B2

公开(公告)日：2016-07-05

申请号：US13611653

申请日：2012-09-12

申请人： Jacek Korec ,  John Manning Savidge Neilson ,  Sameer Pendharkar

发明人： Jacek Korec ,  John Manning Savidge Neilson ,  Sameer Pendharkar

IPC分类号： H01L29/739 ,  H01L21/331 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/66333 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32053 ,  H01L29/0834 ,  H01L29/7395

摘要： Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.

摘要翻译： 具有集成电路的具有集成发射极短路的高压IGBT和使用晶片接合或外延硅的外延硅的制造工艺用于控制漂移区厚度和快速开关速度。

公开(公告)号：US08872273B2

公开(公告)日：2014-10-28

申请号：US13567340

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L27/11 ,  H01L27/06 ,  H01L49/02

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

摘要翻译： 一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。 电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。 开关漂移层为晶体管开关提供了扩展的漏极或集电极。 分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。 输入端子耦合到上电阻器和电阻漂移层。 形成包含栅极控制分压器的集成电路的工艺。

公开(公告)号：US20130285137A1

公开(公告)日：2013-10-31

申请号：US13460523

申请日：2012-04-30

申请人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

发明人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

IPC分类号： H01L29/78

CPC分类号： H01L29/0692 ,  H01L29/87

摘要： A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.

摘要翻译： 用于DMOS晶体管的保护电路包括阳极电路，其具有在第二导电类型（310,312）的第一轻掺杂区域内形成并电连接的第一导电类型的第一重掺杂区域（314）。 在第二导电类型（304）的第二重掺杂区域内具有第一导电类型（700）的多个第三重掺杂区域的阴极电路。 第一引线（202）连接到每个第三重掺杂区域（704），并且通过每两个第三重掺杂区域之间的至少三个间隔开的连接（702）连接到第二重掺杂区域。 在阳极电路和阴极电路之间连接有SCR（400,402）。 DMOS晶体管具有连接到阳极电路的漏极（310,312,316）和连接到阴极电路的源极（304）。

公开(公告)号：US20120112275A1

公开(公告)日：2012-05-10

申请号：US13288690

申请日：2011-11-03

申请人： Philipp Steinmann ,  Amitava Chatterjee ,  Sameer Pendharkar

发明人： Philipp Steinmann ,  Amitava Chatterjee ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  G06F17/50

CPC分类号： H01L29/66681 ,  G06F17/5081 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

摘要翻译： 一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。 一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。 一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

公开(公告)号：US20110108914A1

公开(公告)日：2011-05-12

申请号：US13006566

申请日：2011-01-14

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L29/78

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

公开(公告)号：US07883973B2

公开(公告)日：2011-02-08

申请号：US12335756

申请日：2008-12-16

申请人： Seetharaman Sridar ,  Marie Denison ,  Sameer Pendharkar

发明人： Seetharaman Sridar ,  Marie Denison ,  Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L21/2652

摘要： A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.

摘要翻译： 提供形成半导体器件的方法。 提供具有形成在其上的电介质层的衬底。 电介质层覆盖衬底的受保护区域，并且具有暴露衬底的第一未受保护区域的第一开口。 第一掺杂剂通过电介质层中的第一开口注入第一未保护区域，并通过电介质层注入保护区域。

公开(公告)号：US20100264486A1

公开(公告)日：2010-10-21

申请号：US12426717

申请日：2009-04-20

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

摘要： An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.

摘要翻译： 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 梯度场板电介质位于场板部分和垂直漂移区之间。

公开(公告)号：US07772644B2

公开(公告)日：2010-08-10

申请号：US12509922

申请日：2009-07-27

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L29/78

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

公开(公告)号：US07772075B2

公开(公告)日：2010-08-10

申请号：US12509935

申请日：2009-07-27

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。