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公开(公告)号：US07039888B2
公开(公告)日：2006-05-02
申请号：US10728068
申请日：2003-12-04
CPC分类号： H01L28/20 , G01R31/2846 , G01R31/2884 , G01R31/2891 , H01L27/016
摘要： A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.
摘要翻译： 提出了一种方法，其中薄膜电阻器被建模以考虑自热。 该方法包括制造薄膜电阻器并表征薄膜电阻器的热阻，其中热电阻在操作期间占其自身加热。 然后将热阻用于模拟使用薄膜电阻器的集成电路的模型中。
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公开(公告)号：US20050124079A1
公开(公告)日：2005-06-09
申请号：US10728068
申请日：2003-12-04
CPC分类号： H01L28/20 , G01R31/2846 , G01R31/2884 , G01R31/2891 , H01L27/016
摘要： A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.
摘要翻译： 提出了一种方法，其中薄膜电阻器被建模以考虑自热。 该方法包括制造薄膜电阻器并表征薄膜电阻器的热阻，其中热电阻在操作期间占其自身加热。 然后将热阻用于模拟使用薄膜电阻器的集成电路的模型中。
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公开(公告)号：US20120112275A1
公开(公告)日：2012-05-10
申请号：US13288690
申请日：2011-11-03
CPC分类号： H01L29/66681 , G06F17/5081 , H01L29/0878 , H01L29/1045 , H01L29/161 , H01L29/167 , H01L29/66659 , H01L29/66734 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L29/861
摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
摘要翻译： 一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。 一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。 一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。
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公开(公告)号：US08592900B2
公开(公告)日：2013-11-26
申请号：US13288690
申请日：2011-11-03
IPC分类号： H01L21/00
CPC分类号： H01L29/66681 , G06F17/5081 , H01L29/0878 , H01L29/1045 , H01L29/161 , H01L29/167 , H01L29/66659 , H01L29/66734 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L29/861
摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
摘要翻译： 一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。 一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。 一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。
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5.发明申请Silicide block isolated junction field effect transistor source, drain and gate 有权硅化物阻隔隔离结场效应晶体管源极，漏极和栅极公开(公告)号：US20080026515A1
公开(公告)日：2008-01-31
申请号：US11493229
申请日：2006-07-26
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0642 , H01L29/66901
摘要： An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.
摘要翻译： 结型场效应晶体管（JFET）用形成栅极，源极和漏极区域的图案化硅化物块（SBLK）材料制成。 以这种方式利用硅化物块有助于通过抑制表面状态的影响来减少与JFET相关的低频（闪烁）噪声。
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6.发明授权公开(公告)号：US07217322B2
公开(公告)日：2007-05-15
申请号：US10934188
申请日：2004-09-02
申请人： Jeffrey A. Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
发明人： Jeffrey A. Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
IPC分类号： C30B25/04
CPC分类号： C23C16/42 , C23C16/56 , H01L21/02532 , H01L21/02576
摘要： A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.
摘要翻译： 制造用于集成半导体器件的外延硅 - 锗层的方法包括沉积砷原位掺杂硅 - 锗层的步骤，其中砷和锗随后在沉积期间被引入所述硅 - 锗层的不同区域 所述硅 - 锗层。 通过从锗中分离砷，可避免在沉积过程中砷和锗之间的相互作用，从而允许制造具有可重复掺杂分布的硅 - 锗层。
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公开(公告)号：US20050258990A1
公开(公告)日：2005-11-24
申请号：US11182981
申请日：2005-07-15
IPC分类号： H01L21/02 , H01L21/768 , H01L23/34 , H01L23/525 , H03M1/10
CPC分类号： H01L21/76886 , H01L21/76888 , H01L23/345 , H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.
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8.发明授权公开(公告)号：US08932942B2
公开(公告)日：2015-01-13
申请号：US12729682
申请日：2010-03-23
CPC分类号： H01L21/743 , H01L21/02532 , H01L21/02639 , H01L21/84
摘要： Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.
摘要翻译： 在支撑晶片和绝缘体上硅晶片的顶部硅层的表面之间形成电接触的方法。 该方法包括将空腔蚀刻到顶部硅层和绝缘体层中。 执行选择性外延步骤，以在空腔内生长直到顶部硅层的表面的硅外延层。 一种电气装置，其包括根据本发明方法形成的在支撑晶片和绝缘体上硅晶片的顶部硅层的表面之间的电接触。
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9.发明授权Silicide block isolated junction field effect transistor source, drain and gate 有权硅化物阻隔隔离结场效应晶体管源极，漏极和栅极公开(公告)号：US07670890B2
公开(公告)日：2010-03-02
申请号：US11493229
申请日：2006-07-26
IPC分类号： H01L29/80 , H01L21/337
CPC分类号： H01L29/808 , H01L29/0642 , H01L29/66901
摘要： An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.
摘要翻译： 结型场效应晶体管（JFET）用形成栅极，源极和漏极区域的图案化硅化物块（SBLK）材料制成。 以这种方式利用硅化物块有助于通过抑制表面状态的影响来减少与JFET相关的低频（闪烁）噪声。
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公开(公告)号：US20100032804A1
公开(公告)日：2010-02-11
申请号：US12537246
申请日：2009-08-06
IPC分类号： H01L21/331 , H01L29/73
CPC分类号： H01L29/7378 , H01L21/76283 , H01L29/1004 , H01L29/161 , H01L29/66234 , H01L29/66242 , H01L29/732
摘要： High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.
摘要翻译： 由于Kirk效应，用BiCMOS工艺制造的高电压双极型晶体管在高电流密度下表现出减小的增益。 Kirk效应开始的阈值电流密度由于高电压操作所需的较低掺杂密度而降低。 由于Kirk效应，在高集电极电流密度下扩大的基极区域横向扩展到具有高密度复合位点的区域，导致基极电流增加和增益下降。 本发明在IC中提供了具有不显着增加基极 - 发射极电容的构造中的扩展的非硅化基极外部区域的双极晶体管。 可以使用硅化物阻挡层或发射极 - 基极介电层的延伸区域来实现基极外部区域的横向延伸。 还公开了利用本发明的双极晶体管制造IC的方法。
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