公开(公告)号：US10410946B2

公开(公告)日：2019-09-10

申请号：US15871793

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Naohito Suzumura ,  Hideki Aono

IPC: H01L29/76 ,  H01L23/367 ,  H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/118

Abstract: A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

公开(公告)号：US10438861B2

公开(公告)日：2019-10-08

申请号：US15280308

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Hideki Aono ,  Makoto Ogasawara ,  Naohito Suzumura ,  Tetsuya Yoshida

IPC: H01L21/66 ,  G01R31/26 ,  H01L29/78

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

公开(公告)号：US09391606B2

公开(公告)日：2016-07-12

申请号：US14506621

申请日：2014-10-04

Applicant: Renesas Electronics Corporation

Inventor： Noritaka Fukuo ,  Hideki Aono ,  Eiichi Murakami

IPC: H03L7/00 ,  H03K17/284 ,  H03K17/30

CPC classification number: H03K17/284 ,  H03K17/145 ,  H03K17/302

Abstract: An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor.

Abstract translation: 防止P沟道MOS晶体管的NBTI故障。 半导体集成电路装置包括复位脉冲控制单元RPC。 复位脉冲控制单元RPC产生复位脉冲RP，以从在待机状态下接收晶体管的栅极处的负电压的MOS晶体管的NBTI引起的劣化恢复。 在产生的复位脉冲RP被输入到MOS晶体管的栅极之后，用于激活MOS晶体管的动作控制信号ACC被输入到MOS晶体管的栅极以激活晶体管。

公开(公告)号：US10651094B2

公开(公告)日：2020-05-12

申请号：US16291620

申请日：2019-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki Aono ,  Tetsuya Yoshida ,  Makoto Ogasawara ,  Shinichi Okamoto

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/265 ,  H01L29/66

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.