公开(公告)号：US10886379B2

公开(公告)日：2021-01-05

申请号：US16055050

申请日：2018-08-04

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Yoshida

IPC: H01L29/51 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8238

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.

公开(公告)号：US10325899B2

公开(公告)日：2019-06-18

申请号：US15880212

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Keiichi Maekawa ,  Hideaki Yamakoshi ,  Shinichiro Abe ,  Hideki Makiyama ,  Tetsuya Yoshida ,  Yuto Omizu

IPC: G11C16/04 ,  H01L27/02 ,  G11C16/12 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11573

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

公开(公告)号：US11915975B2

公开(公告)日：2024-02-27

申请号：US17480746

申请日：2021-09-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Yoshida ,  Tomohiro Tomizawa

IPC: H01L21/768 ,  H01L21/66 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/76805 ,  H01L22/32 ,  H01L27/1203 ,  H01L29/66568

Abstract: A first MISFET is formed on a semiconductor layer of an SOI substrate in a circuit region and a second MISFET composing a TEG for VC inspection is formed on the semiconductor layer of the SOI substrate in a TEG region. An interlayer insulating film is formed, contact holes are formed in the interlayer insulating film, and plugs are formed in the contact holes, respectively. In the TEG region, the plugs include a plug electrically connected to both the semiconductor substrate composing the SOI substrate and the semiconductor layer composing the SOI substrate.

公开(公告)号：US10103075B2

公开(公告)日：2018-10-16

申请号：US15630725

申请日：2017-06-22

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Tetsuya Yoshida ,  Koetsu Sawai

IPC: H01L23/58 ,  H01L21/66 ,  H01L21/84 ,  H01L21/265 ,  H01L21/768 ,  H01L27/12 ,  H01L23/535 ,  H01L23/544 ,  H01L27/11 ,  G01R31/307

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

公开(公告)号：US09299720B2

公开(公告)日：2016-03-29

申请号：US14470846

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Tetsuya Yoshida ,  Koetsu Sawai

IPC: H01L23/58 ,  H01L27/12 ,  H01L21/768 ,  H01L27/11 ,  H01L21/66

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

Abstract translation: 当执行用于TEG的VC检查时，通过增加接触插塞的发射强度容易地检测是否发生接触插塞的任何故障，从而提高了半导体器件的可靠性。 SRAM的元件结构形成在芯片区域的SOI衬底上。 此外，在TEG区域中，在从SOI层和BOX膜露出的半导体衬底上形成接触插塞连接到半导体衬底的SRAM的元件结构，作为用于VC检查的TEG。

公开(公告)号：US10438861B2

公开(公告)日：2019-10-08

申请号：US15280308

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Hideki Aono ,  Makoto Ogasawara ,  Naohito Suzumura ,  Tetsuya Yoshida

IPC: H01L21/66 ,  G01R31/26 ,  H01L29/78

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

公开(公告)号：US11239337B2

公开(公告)日：2022-02-01

申请号：US17110493

申请日：2020-12-03

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Yoshida

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8238

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.

公开(公告)号：US10651094B2

公开(公告)日：2020-05-12

申请号：US16291620

申请日：2019-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki Aono ,  Tetsuya Yoshida ,  Makoto Ogasawara ,  Shinichi Okamoto

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/265 ,  H01L29/66

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

公开(公告)号：US20180286850A1

公开(公告)日：2018-10-04

申请号：US15880212

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Keiichi Maekawa ,  Hideaki Yamakoshi ,  Shinichiro Abe ,  Hideki Makiyama ,  Tetsuya Yoshida ,  Yuto Omizu

IPC: H01L27/02 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/12

CPC classification number: H01L27/0207 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

公开(公告)号：US09721857B2

公开(公告)日：2017-08-01

申请号：US15067173

申请日：2016-03-10

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Tetsuya Yoshida ,  Koetsu Sawai

IPC: H01L23/58 ,  H01L21/66 ,  H01L27/12 ,  H01L21/768 ,  H01L27/11 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.