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公开(公告)号：US20090159934A1
公开(公告)日：2009-06-25
申请号：US12274758
申请日：2008-11-20
IPC分类号： H01L29/80 , H01L21/335
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译： 通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。 在形成与栅电极相邻的间隔层之后，栅电极变薄。 此外，间隔层的高度也可以减小。 间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。 减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。 升高的源极/漏极层可以位于本征源极/漏极区域上。 凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。 此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。
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公开(公告)号：US08492803B2
公开(公告)日：2013-07-23
申请号：US12274758
申请日：2008-11-20
IPC分类号： H01L29/80 , H01L21/335
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译： 通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。 在形成与栅电极相邻的间隔层之后，栅电极变薄。 此外，间隔层的高度也可以减小。 间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。 减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。 升高的源极/漏极层可以位于本征源极/漏极区域上。 凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。 此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。
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公开(公告)号：US07459382B2
公开(公告)日：2008-12-02
申请号：US11308432
申请日：2006-03-24
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译： 通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。 在形成与栅电极相邻的间隔层之后，栅电极变薄。 此外，间隔层的高度也可以减小。 间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。 减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。 升高的源极/漏极层可以位于本征源极/漏极区域上。 凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。 此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。
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公开(公告)号：US20070221964A1
公开(公告)日：2007-09-27
申请号：US11308432
申请日：2006-03-24
IPC分类号： H01L29/76
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译： 通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。 在形成与栅电极相邻的间隔层之后，栅电极变薄。 此外，间隔层的高度也可以减小。 间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。 减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。 升高的源极/漏极层可以位于本征源极/漏极区域上。 凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。 此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。
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5.发明授权Semiconductor device structure having low and high performance devices of same conductive type on same substrate 失效具有相同基板上相同导电类型的低和高性能器件的半导体器件结构公开(公告)号：US07776695B2
公开(公告)日：2010-08-17
申请号：US11306716
申请日：2006-01-09
申请人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
发明人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/0922 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.
摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域 栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。
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6.发明申请STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE 审中-公开具有应力硅化物的应变FinFET的结构和方法公开(公告)号：US20080173942A1
公开(公告)日：2008-07-24
申请号：US11625431
申请日：2007-01-22
申请人： Huilong Zhu , Siddhartha Panda , Jay W. Strane , Sey-Ping Sun , Brian L. Tessier
发明人： Huilong Zhu , Siddhartha Panda , Jay W. Strane , Sey-Ping Sun , Brian L. Tessier
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A stressed semiconductor structure including at least one FinFET device on a surface of a substrate, typically a buried insulating layer of an initial semiconductor-on-insulator substrate, is provided. In a preferred embodiment, the at least one FinFET device includes a semiconductor Fin that is located on an unetched portion of the buried insulator layer which has a raised height as compared to an adjacent and adjoining etched portion of the buried insulating layer. The semiconductor Fin includes a gate dielectric on its sidewalls and optionally a hard mask located on an upper surface thereof. The inventive structure also includes a gate conductor, which is located on the surface of the substrate, typically the buried insulating layer, and the gate conductor is at least laterally adjacent to the gate dielectric located on the sidewalls of the semiconductor Fin. A stressed silicide is located on the gate conductor, which introduces stress into the channel of the FinFET device. The stressed silicide memorizes the stress from a sacrificial stressed film that is formed prior to forming the stressed silicide. The stress type of the stressed film is introduced into the silicide during a silicide anneal step.
摘要翻译： 提供了一种应力半导体结构，其包括在衬底的表面上的至少一个FinFET器件，通常是初始绝缘体上半导体衬底的掩埋绝缘层。 在优选实施例中，所述至少一个FinFET器件包括位于所述掩埋绝缘体层的未蚀刻部分上的半导体Fin，所述半导体Fin与所述掩埋绝缘层的相邻和相邻蚀刻部分相比具有升高的高度。 半导体鳍包括其侧壁上的栅极电介质和任选地位于其上表面上的硬掩模。 本发明的结构还包括栅极导体，其位于衬底的表面上，通常为掩埋绝缘层，并且栅极导体至少横向邻近位于半导体Fin的侧壁上的栅极电介质。 应力硅化物位于栅极导体上，其将应力引入FinFET器件的沟道中。 应力硅化物记忆在形成应力硅化物之前形成的牺牲应力膜的应力。 在硅化物退火步骤期间，将应力膜的应力类型引入到硅化物中。
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7.发明申请SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVICES OF SAME CONDUCTIVE TYPE ON SAME SUBSTRATE 失效具有相同基板上的相同导电类型的低性能和高性能器件的半导体器件结构公开(公告)号：US20070158753A1
公开(公告)日：2007-07-12
申请号：US11306716
申请日：2006-01-09
申请人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
发明人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/0922 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.
摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域 栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。
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公开(公告)号：US07687829B2
公开(公告)日：2010-03-30
申请号：US12144250
申请日：2008-06-23
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译： 提供了具有改进的载流子迁移率的半导体结构。 半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。 本发明还提供了制造该方法的方法。 一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道 。
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公开(公告)号：US20080179627A1
公开(公告)日：2008-07-31
申请号：US11669902
申请日：2007-01-31
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848 , H01L29/78687
摘要： NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.
摘要翻译： 公开了具有单独应变通道区域的NMOS和PMOS器件结构及其制造方法。 NMOS器件的源极和漏极由引起NMOS器件沟道在拉伸方向上的应变移动的材料外延生长。 而PMOS器件的源极和漏极是外延生长的，这种材料导致PMOS器件沟道在压缩方向上的应变移动。
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公开(公告)号：US20080090370A1
公开(公告)日：2008-04-17
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
IPC分类号： H01L21/331
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.
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