摘要:
NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.
摘要:
NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.
摘要:
A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.
摘要:
In all representative embodiments presented, the Ge concentration in the source and drain 10 and the SiGe epitaxial channel layer 20 is in the 15% to 50% range, preferably between about 20% to 40%. The SiGe thicknesses in the source/drain 10 are staying below the critical thickness for the given Ge concentration. The critical thickness is defined such that above it the SiGe will relax and defects and dislocations will form. The thickness of the SiGe epitaxial layer 20 typically is between about 5nm and 15nm. The thickness of the epitaxial Si layer 30 is typically between about 5nm and 15nm. FIG. 1A shows an embodiment where the body is bulk Si. These type of devices are the most common devices in present day microelectronics. FIGS. 1B and 1C show representative embodiment of the heterojunction source/drain FET device when the Si body 40 is disposed on top of an insulating material 55. This type of technology is commonly referred to as silicon on insulator (SOI) technology. The insulator material 55 usually, and preferably, is SiO2. FIG. 1B shows an SOI embodiment where the body 40 has enough volume to contain mobile charges. Such SOI devices are called partially depleted devices. FIG. 1C shows an SOI embodiment where the volume of the body 40 is insufficient to contain mobile charges. Such SOI devices are called fully depleted devices. For devices shown in FIG. 1B and 1C there is, at least a thin, layer of body underneath the source and drain 10. This body material serves as the seed material onto which the epitaxial SiGe source and drain 10 are grown. In an alternate embodiment, shown in FIG. 1D. for extremely thin fully depleted SOI devices, one could grow the source and drain 10 laterally, from a lateral seeding, in which case the source and drain 10 would penetrate all the way down to the insulating layer 55.
摘要:
A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.
摘要:
A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.
摘要:
A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.
摘要:
A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a heterojunction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the heterojunction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.
摘要:
At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
摘要:
A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.