-
公开(公告)号：US20210383871A1
公开(公告)日：2021-12-09
申请号：US16893866
申请日：2020-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN , Evgeny Blaichman
Abstract: A method, apparatus, non-transitory computer readable medium, and system for selecting program voltages for a memory device are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may map a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters, program the set of information bits into the one or more memory cells based on the mapping, detect the voltage levels of the one or more memory cells to generate one or more detected voltage levels, and identify a set of predicted information bits based on the one or more detected voltage levels using a neural network comprising a plurality of network parameters, wherein the network parameters are trained together with the embedding parameters.
-
公开(公告)号：US20210019082A1
公开(公告)日：2021-01-21
申请号：US16514195
申请日：2019-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN , ARIEL DOUBCHAK , NOAM LIVNE
Abstract: A memory system including a nonvolatile memory (NVM) device and a controller is provided. The NVM device includes a main region and a spare region. The controller writes write data to a selected row of the main region, determines whether the written row is bad, and writes the write data to a spare address in the spare region and writes the spare address to the bad row, when the written row is determined to be bad.
-
公开(公告)号：US20230238074A1
公开(公告)日：2023-07-27
申请号：US18295130
申请日：2023-04-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN
CPC classification number: G11C29/42 , G11C29/44 , G11C7/1039 , G11C29/40
Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.
-
公开(公告)号：US20220293192A1
公开(公告)日：2022-09-15
申请号：US17197617
申请日：2021-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN , Evgeny Blaichman , Ron Golan , Sergey Gendel
Abstract: Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range.
-
公开(公告)号：US20220013189A1
公开(公告)日：2022-01-13
申请号：US16923334
申请日：2020-07-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN , EVGENY BLAICHMAN , RON GOLAN , SERGEY GENDEL
Abstract: A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.
-
Patent Agency Ranking
公开(公告)号：US20240157933A1
公开(公告)日：2024-05-16
申请号：US18511690
申请日：2023-11-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN , SARIT BUZAGLO , ARIEL DOUBCHAK
Abstract: A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector αv(l) of soft information from a parent node; computing a vector αvl(l) of soft information for a left child of node v; providing node v with a vector βvl(l) of hard decisions from the left child and using it with αv(l) to create a soft information vector αv(l) and passing it to a right child of node v; providing node v with a vector βvr(l) of hard decisions from its right child and using it with βvl(l) to create a hard decision vector, βv of hard decisions, and passing it to its parent node; updating, when v is a ith leaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.
-
公开(公告)号：US20240154627A1
公开(公告)日：2024-05-09
申请号：US17983646
申请日：2022-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： DIKLA SHAPIRO , AMIT BERMAN
CPC classification number: H03M13/1515 , H03M13/1111 , H03M13/1525
Abstract: A method of operation for a Reed-Solomon decoder includes receiving partial input data of symbols of a Reed-Solomon codeword; updating Reed-Solomon syndromes and error location polynomial coefficients based on the partial input data; maintaining the Reed-Solomon syndromes and the error location polynomial coefficients in a memory prior to starting activation of Reed-Solomon decoding; and inputting the Reed-Solomon syndromes and the error location polynomial coefficients to a first activation of Reed-Solomon decoding including calculating an initial error evaluator polynomial as a first error evaluator polynomial, performing error detection based on the first error evaluator polynomial to determine presence and location of errors in an input Reed-Solomon codeword, and updating the error location polynomial when errors are found in the input Reed-Solomon codeword. The error location polynomial coefficients in the memory are updated during each activation of Reed-Solomon decoding when at least one error is identified in the Reed-Solomon codeword.
-
公开(公告)号：US20210344356A1
公开(公告)日：2021-11-04
申请号：US16865891
申请日：2020-05-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN , ARIEL DOUBCHAK , ELI HAIM , EVGENY BLAICHMAN
IPC: H03M13/15 , H03M13/39 , H03M13/11 , G11C11/408 , G11C11/4074 , G11C7/02 , G06N3/08
Abstract: A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.
-
公开(公告)号：US20210096751A1
公开(公告)日：2021-04-01
申请号：US16585186
申请日：2019-09-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN , ELISHA HALPERIN , EVGENY BLAICHMAN
Abstract: A memory system includes a memory device, and a memory controller including a processor and an internal memory. A computer program including a neural network is stored in the memory system. The processor executes the computer program to extract a voltage level from each of a plurality of memory cells connected to one string select line (SSL), in which the memory cells and the SSL are included in a memory block of the memory device, provide the voltage levels as input to the neural network, and perform noise cancellation on the SSL, using the neural network, by changing at least one of the voltage levels from a first voltage level to a second voltage level. The first voltage level is classified into a first cluster of memory cells, and the second voltage level is classified into a second cluster of memory cells different from the first cluster.
-
公开(公告)号：US20200335164A1
公开(公告)日：2020-10-22
申请号：US16388092
申请日：2019-04-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AMIT BERMAN
IPC: G11C13/00
Abstract: A method for writing memory cells including: applying a program voltage to a target wordline; grounding bitlines of memory cells to be written to a first resistance state; setting a bitline voltage of unselected bitlines; and setting a wordline voltage of unselected wordlines; applying the program voltage to a target bitline; grounding wordlines of the memory cells to be written to a second resistance state; setting the wordline voltage of the unselected wordlines to a first value if a peak of a maximum voltage drop is greater than or equal to a second value; otherwise, setting the wordline voltage to zero; and setting the bitline voltage of the unselected bitlines to a third value if the peak of the maximum voltage drop is greater than or equal to the second value; otherwise, setting the bitline voltage to zero.
-
-
-
-
-
-
-
-
-
Search Results
15
records
(took 0.015 seconds)
