公开(公告)号：US20230088827A1

公开(公告)日：2023-03-23

申请号：US17945538

申请日：2022-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hyunjae LEE ,  Dukhyun CHOE ,  Jinseong HEO

IPC: H01L29/51 ,  H01L29/78

Abstract: A semiconductor device includes: a first source/drain region; a second source/drain region; a channel between the first source/drain region and the second source/drain region; an interfacial insulating layer on the channel; a ferroelectric layer on the interfacial insulating layer; and a gate electrode on the ferroelectric layer, wherein, when a numerical value of dielectric constant of the interfacial insulating layer is K and a numerical value of remnant polarization of the ferroelectric layer is Pr, a material of the interfacial insulating layer and a material of the ferroelectric layer are selected so that K/Pr is 1 or more.

公开(公告)号：US20220058081A1

公开(公告)日：2022-02-24

申请号：US17407028

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

Inventor： Kwonjong LEE ,  Sanghyo KIM ,  Hyojin LEE ,  Minyoung CHUNG ,  Yongsung KIL ,  Seungil PARK ,  Seunghyun LEE ,  Hyunjae LEE

IPC: G06F11/10 ,  H04L1/00 ,  G06N3/02

Abstract: Provided is a 5th generation (5G) or 6th generation (6G) communication system for supporting higher data rates after 4G communication systems such as long term evolution (LTE). A communication method of a user equipment (UE) includes receiving, from a base station (BS), information about a decoding mode including bit information corresponding to the number of times of perturbation, receiving data from the BS on a Physical Downlink Shared Channel (PDSCH), and decoding the received data based on the information about the decoding mode, wherein the information about the decoding mode may be generated based on service information including at least one of Quality of Service (QoS), a service priority, packet delay performance, packet error probability performance, a requirement, or a data transmission scheme.

公开(公告)号：US20190055649A1

公开(公告)日：2019-02-21

申请号：US16030323

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyoung Lee ,  Hyunjae LEE ,  lk Soo KIM ,  Jang-Hee LEE

IPC: C23C16/455 ,  C23C16/44 ,  H01L21/02

Abstract: Provided are a precursor supply unit, a substrate processing system, and a method of fabricating a semiconductor device using the same. The precursor supply unit may include an outer container, an inner container provided in the outer container and used to store a precursor source, a gas injection line having an injection port, which is provided below the inner container and in the outer container and is used to provide a carrier gas into the outer container, and a gas exhaust line having an exhaust port, which is provided below the inner container and in the outer container and is used to exhaust the carrier gas in the outer container and a precursor produced from the precursor source.

公开(公告)号：US20250126875A1

公开(公告)日：2025-04-17

申请号：US18913129

申请日：2024-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Seunggeol NAM ,  Donghoon KIM ,  Sijung YOO ,  Dukhyun CHOE

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: Provided is a semiconductor device including a channel layer including a semiconductor material, a ferroelectric layer arranged on the channel layer and including a ferroelectric material, a gate electrode arranged on the ferroelectric layer, a first insertion layer arranged between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer arranged between the channel layer and the ferroelectric layer and including a second paraelectric material having a dielectric constant higher than a dielectric constant of the first paraelectric material.

公开(公告)号：US20240172447A1

公开(公告)日：2024-05-23

申请号：US18491161

申请日：2023-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Hyunjae LEE ,  Dukhyun CHOE

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

Abstract: Provided is a three-dimensional (3D) ferroelectric memory device. The 3D ferroelectric memory device includes a substrate, a plurality of insulating layers stacked on the substrate, a plurality of gate electrodes between the plurality of insulating layers, a plurality of gate insulating layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of gate insulating layers, a ferroelectric layer in contact with the plurality of intermediate electrodes and the plurality of insulating layers, and a channel layer in contact with the ferroelectric layer.

公开(公告)号：US20230275150A1

公开(公告)日：2023-08-31

申请号：US18168699

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Jinseong HEO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE

IPC: H01L29/78 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L29/7606

Abstract: A semiconductor device may include a semiconductor substrate including a dopant having a polarity; a channel layer on the semiconductor substrate and including majority carriers having a polarity opposite to a polarity of the semiconductor substrate; a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. A doping concentration of the semiconductor substrate may be less than a concentration of the majority carrier of the channel layer.

公开(公告)号：US20250126803A1

公开(公告)日：2025-04-17

申请号：US18913098

申请日：2024-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Sijung YOO ,  Minhyun LEE ,  Hyunjae LEE ,  Seokhoon CHOI

IPC: H10B51/30 ,  H10B51/20

Abstract: A semiconductor device, and a memory apparatus and an electronic apparatus including the same are provided. The semiconductor device may include a gate electrode, a ferroelectric layer on the gate electrode, a channel layer on the ferroelectric layer, and a plurality of nanostructures spaced apart from each other in the ferroelectric layer. The plurality of nanostructures may be adjacent to the gate electrode or the channel layer, or a portion of the plurality of nanostructures may be adjacent to the gate electrode and the rest portion of the plurality of nanostructures may be adjacent to the channel layer.

公开(公告)号：US20250126802A1

公开(公告)日：2025-04-17

申请号：US18761688

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sijung YOO ,  Seunggeol NAM ,  Donghoon KIM ,  Hyunjae LEE ,  Dukhyun CHOE ,  Seokhoon CHOI

IPC: H10B51/30 ,  G06N3/063 ,  H01L29/51 ,  H01L29/78

Abstract: A ferroelectric field effect transistor includes a channel, a gate electrode provided to face the channel, a ferroelectric layer provided between the channel and the gate electrode, an interfacial layer provided between the channel and the ferroelectric layer, and a diffusion barrier layer provided between the ferroelectric layer and the gate electrode, wherein the diffusion barrier layer includes SiON, the diffusion barrier layer has an oxygen concentration gradient that gradually decreases from a first surface of the diffusion barrier layer facing the gate electrode toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and the diffusion barrier layer may have a nitrogen concentration gradient that gradually increases from the first surface toward the second surface.

公开(公告)号：US20240015983A1

公开(公告)日：2024-01-11

申请号：US18340560

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H10B53/20 ,  H10B53/30

CPC classification number: H10B53/20 ,  H10B53/30

Abstract: A three-dimensional (3D) ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate, a plurality of ferroelectric layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers, a gate insulating layer in contact with the plurality of intermediate electrodes, and a channel layer in contact with the gate insulating layer. Widths of the intermediate electrodes may be greater than widths of the ferroelectric layers in contact with the intermediate electrodes.

公开(公告)号：US20240008289A1

公开(公告)日：2024-01-04

申请号：US18340407

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H10B53/20 ,  H10B53/30

CPC classification number: H10B53/20 ,  H10B53/30

Abstract: Provided is a 3D ferroelectric memory device. The 3D ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate in a first direction; a plurality of ferroelectric layers on the plurality of gate electrodes in a second direction; a plurality of intermediate electrodes on the plurality of ferroelectric layers in the second direction; a first insulating layer between the plurality of gate electrodes and between the plurality of intermediate electrodes; a second insulating layer on the plurality of intermediate electrodes and the first insulating layer; and a channel layer on the second insulating layer.