公开(公告)号：US11804841B2

公开(公告)日：2023-10-31

申请号：US17569041

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin Choi ,  Yonghun Kim ,  Jinhyeok Baek ,  Yoochang Sung ,  Changsik Yoo ,  Jeongdon Ihm

IPC: H03K19/003 ,  G11C7/22 ,  G11C5/14 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/06

CPC classification number: H03K19/00384 ,  G11C5/147 ,  G11C7/22 ,  H03K19/018521 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/06

Abstract: An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

公开(公告)号：US10069495B2

公开(公告)日：2018-09-04

申请号：US15594107

申请日：2017-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hangi Jung ,  Hun-Dae Choi ,  Jinhyeok Baek

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4076 ,  G11C11/408

Abstract: A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.